Using the Gate-Diffusion Input Technique for Low-Power Programmable Logic Array Design
A novel low-power programmable logic array (PLA) structure based on gate diffusion input (GDI) is presented. The GDI technique allows reducing power consumption, propagation delay, and area of digital circuits. It also maintains low complexity of circuit design. In this chapter, we use the GDI technique to modify Kwang’s PLAs. The conditional evaluation circuit in all product lines of Kwang’s PLAs is replaced by a GDI circuit. To verify the proposed PLA, we use the MCNC PLA benchmark circuits to perform experiments. Simulation results show that the proposed scheme can reduce the number of transistors by 28.1 %, power consumption by 40.6 %, delay time by 15 %, and total power-delay product (PDP) by 49.5 % compared with Kwang’s PLAs, which use the alu2 in MCNC benchmark for 0.18μm CMOS technology.
KeywordsLow-power CMOS Programmable logic array Gate diffusion input
- 1.Posluszny S et al (1998) Design methodology for a 1.0 GHz micro processor. In: International conference on computer design: VLSI in computers and processors, ICCD 1998, pp 17–23Google Scholar
- 2.Weste N, Eshrahian K (1992) Principles of CMOS VLSI design-a system perspective, 2nd edn. Addison-Wesley, ReadingGoogle Scholar
- 4.Oh KI, Kim LS (1994) A high performance low power dynamic PLA with conditional evaluation scheme. Proc IEEE Int Symp Circ Syst 2:881–884Google Scholar