Circuit Design for Ultra Low-Noise and Low-Power Sensor Interface

Abstract

This chapter presents a neural recording amplifier array suitable for large-scale integration with multi-electrode arrays (MEAs) in very low-power microelectronic cortical implants. The proposed amplifier is one of the most energy-efficient structures reported to date, which theoretically achieves an effective noise efficiency factor (NEF) smaller than the limit that can be achieved by any existing amplifier topology which utilize a CMOS differential pair input stage. The proposed architecture , which is referred to as partial OTA sharing architecture, results in a significant reduction of power dissipation as well as silicon area, in addition to a very low NEF. The effect of mismatch on crosstalk between channels and the trade-off between noise and crosstalk are theoretically analyzed. Moreover, a mathematical model of the nonlinearity of the amplifier is derived, and its accuracy is confirmed by simulations and measurements. For an array of four neural amplifiers, measurement results show a midband gain of 39.4 dB and a $-3$ dB bandwidth ranging from 10 Hz to 7.2 kHz. The input-referred noise integrated from 10 Hz to 100 kHz is measured at $3.5\,\upmu \mathrm{{V}}_{\mathrm{{rms}}}$ and the power consumption is $7.92\,\upmu \mathrm{{W}}$ from a 1.8 V supply, which corresponds to $\mathrm{NEF}=3.35$. The worst-case crosstalk and CMRR within the desired bandwidth are $-43.5$ dB and 70.1 dB, respectively, and the active silicon area of each amplifier is $256\,\upmu \mathrm{{m}}\times 256\,\upmu \mathrm{{m}}$ in a $0.18\,\upmu \mathrm{{m}}$ CMOS technology.