Wireless Cortical Implantable Systems pp 43-65 | Cite as

# Circuit Design for Ultra Low-Noise and Low-Power Sensor Interface

## Abstract

This chapter presents a neural recording amplifier array suitable for large-scale integration with multi-electrode arrays (MEAs) in very low-power microelectronic cortical implants. The proposed amplifier is one of the most energy-efficient structures reported to date, which theoretically achieves an effective noise efficiency factor (NEF) smaller than the limit that can be achieved by any existing amplifier topology which utilize a CMOS differential pair input stage. The proposed architecture , which is referred to as partial OTA sharing architecture, results in a significant reduction of power dissipation as well as silicon area, in addition to a very low NEF. The effect of mismatch on crosstalk between channels and the trade-off between noise and crosstalk are theoretically analyzed. Moreover, a mathematical model of the nonlinearity of the amplifier is derived, and its accuracy is confirmed by simulations and measurements. For an array of four neural amplifiers, measurement results show a midband gain of 39.4 dB and a \(-3\) dB bandwidth ranging from 10 Hz to 7.2 kHz. The input-referred noise integrated from 10 Hz to 100 kHz is measured at \(3.5\,\upmu \mathrm{{V}}_{\mathrm{{rms}}}\) and the power consumption is \(7.92\,\upmu \mathrm{{W}}\) from a 1.8 V supply, which corresponds to \(\mathrm{NEF}=3.35\). The worst-case crosstalk and CMRR within the desired bandwidth are \(-43.5\) dB and 70.1 dB, respectively, and the active silicon area of each amplifier is \(256\,\upmu \mathrm{{m}}\times 256\,\upmu \mathrm{{m}}\) in a \(0.18\,\upmu \mathrm{{m}}\) CMOS technology.

### References

- 1.IEEE standard for safety levels with respect to human exposure to radio frequency electromagnetic fields, 3 kHz to 300 GHz IEEE Std. C95.1-2005 (2006)Google Scholar
- 2.Silay KM, Dehollain C, Declercq M (2008) Numerical analysis of temperature elevation in the head due to power dissipation in a cortical implant. In: Proceedings of the IEEE EMBC’08, pp 951–956Google Scholar
- 3.Nordhausen CT, Maynard EM, Normann RA (1996) Single unit recording capabilities of a 100-microelectrode array. Brain Res 726:129–140CrossRefGoogle Scholar
- 4.Steyaert M, Sansen W, Zhongyuan C (1987) A micropower low-noise monolithic instrumentation amplifier for medical purposes. IEEE J Solid-State Circuits 22(6):1163–1168Google Scholar
- 5.Enz CC, Temes GC (1996) Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization. Proc IEEE 84(11):1584–1614CrossRefGoogle Scholar
- 6.Mohseni P, Najafi K (2004) A fully integrated neural recording amplifier with DC input stablization. IEEE Trans Biomed Eng 51(5):832–837CrossRefGoogle Scholar
- 7.Gosselin B, Sawan M, Chapman CA (2007) A low-power integrated bioamplifier with active low-frequency suppression. IEEE Trans Biomed Circuits Syst 1(3):pp 184–192Google Scholar
- 8.Harrison RR, Charles C (2003) A low-power low-noise CMOS amplifier for neural recording applications. IEEE J Solid-State Circuits 38(6):958–965CrossRefGoogle Scholar
- 9.Wattanapanitch W, Fee M, Sarpeshkar R (2007) An energy-efficient micropower neural recording amplifier. IEEE Trans Biomed Circuits Syst 1(2):136–147CrossRefGoogle Scholar
- 10.Holleman J, Otis B (2007) A sub-microwatt low-noise amplifier for neural recording. In: Proceedings of the IEEE EMBC’07, pp 3930–3933 Aug 2007Google Scholar
- 11.Rai S, Holleman J, Pandey JN, Zhang F, Otis B (2009) A 500\(\mu \)W neural tag with 2\(\mu \)V\(_{rms}\) AFE and frequency-multiplying MICS/ISM FSK transmitter. ISSCC Digest of Technical Papers pp 212–213 Feb 2009Google Scholar
- 12.Jochum T, Denison T, Wolf P (2009) Integrated circuit amplifiers for multi-electrode intracortical recording. J Neural Eng 6(1):1–26CrossRefGoogle Scholar
- 13.Ayers S, Gillis KD, Lindau M, Minch BA (2007) Design of a CMOS potentiostat circuit for electrochemical detector arrays. IEEE Trans Circuits Syst-I 54(4):736–744CrossRefGoogle Scholar
- 14.Majidzadeh V, Schmid A, Leblebici Y (2009) A micropower neural recording amplifier with improved noise efficiency factor. In: Proceedings of the 19th European Conference on Circuit theory and design, pp 319–322 Aug 2009Google Scholar
- 15.Majidzadeh V, Schmid A, Leblebici Y (2011) Energy efficient low-noise neural recording amplifier with enhanced noise efficiency factor. IEEE Trans on Biomed Circuits syst 5(3):262–271Google Scholar
- 16.Enz C, Vittoz E (2006) Charge-based MOS transistor modeling: the EKV model for low-power and RF IC design. Wiley, New YorkGoogle Scholar