Abstract
Since the introduction of the first SPICE simulator in 1973 (Nagel and Pederson 1973), circuit designers use simulators to predict and optimize circuit performance at design time. This results in huge savings in development costs and enables a designer to maximize the performance of his or her circuit in a particular technology. Over time, computer-aided design (CAD) software has become more complex and more and more aspects related to IC development have been modeled and included in circuit simulation tools. As designers try to push their designs to the limit, using technologies with ever-smaller feature sizes, more and more reliability problems pop up. Guaranteeing sufficient product yield under the presence of process variations, for example, have become one of the first major IC reliability issues. To estimate the impact of process variations at design time, EDA companies have started to offer variation-aware simulation methods such as corner simulations or Monte-Carlo (MC) simulations.
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In accordance with the focus of this work, this chapter focuses on tools intended for analog circuit lifetime analysis. Other useful and complementary tools such as the Berkeley Design Automation AFS platform, the Solido Analog\(^+\) Suite, the Muneda WiCkeD toolset or any toolset for digital circuit simulation and verification are not discussed here.
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© 2013 Springer Science+Business Media New York
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Maricau, E., Gielen, G. (2013). Background on IC Reliability Simulation. In: Analog IC Reliability in Nanometer CMOS. Analog Circuits and Signal Processing. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-6163-0_4
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DOI: https://doi.org/10.1007/978-1-4614-6163-0_4
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