Abstract
For over four decades, scientists have been scaling devices to increasingly smaller feature sizes (Lewyn et al. 2009; International technology roadmap for semiconductors 2011). This trend is driven by a seemingly unending demand for ever-better performance and by fierce global competition. The steady CMOS technology downscaling is needed to meet requirements on speed, complexity, circuit density, power consumption and ultimately cost required by many advanced applications. However, going to these ultra-scaled CMOS devices also brings some drawbacks.
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Notes
- 1.
Parametric circuit failures are related to process variations and are circuits that do function but with a performance outside the desired range. Catastrophic circuit failures result from process errors or defects and are described by the functional yield. The latter are not covered in this work.
- 2.
Pelgrom’s model expresses the standard deviation on the difference between the threshold voltages of two matched transistors. The standard deviation on the threshold voltage of a single transistor can be found by dividing \(A_{\mathrm{{VTH}}}\) by \(\sqrt{2}\).
- 3.
Besides TDDB, which is a time-dependent wearout effect, oxide BD can also result from electrical overstress (EOS), electrostatic discharge (ESD) or under the presence of weak spots in the oxide. EOS and ESD involve the application of a high voltage being applied across the oxide. This causes a dramatic increase of the gate current, localized heating and a meltdown of the silicon. Early life BD failures due to weak spots in the oxide are essentially similar to TDDB, but happen within the first year of the circuit operational life. This work focuses aging effects, therefore EOS, ESD and early life failures are not discussed here.
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Maricau, E., Gielen, G. (2013). CMOS Reliability Overview. In: Analog IC Reliability in Nanometer CMOS. Analog Circuits and Signal Processing. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-6163-0_2
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DOI: https://doi.org/10.1007/978-1-4614-6163-0_2
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