Abstract
Circuit synthesis denotes the automated generation of logic networks from behavioral descriptions at an arbitrary level. Synthesis is becoming a key issue in VLSI design for efficient and flexible usage of cell and component. The architectural synthesis involves resource allocation, resource binding, and scheduling tasks. As the capacity of FPGAs increases, synthesis tools and efficient synthesis methods for targeted device become more significant to efficiently exploit the resources and logic capacity. This paper explores a design solution and synthesis optimization constraints for targeted FPGA device. The issue focuses on: the synthesis optimization for various modeling approaches; synthesizer producing sub optimal results for setting the target constraints too high; how an inefficient coding style can adversely impact synthesis and simulation, resulting in slow circuits. All the design solutions are elucidated with appropriate example. The module functionality are described using Verilog HDL and performance issues like slice utilized, simulation time, percentage of logic utilization, level of logic are analyzed at 90 nm process technology using SPARTAN6 XC6SLX150 XILINX ISE12.1 tool.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Wang JX, Loo SM (2010) Case study of finite resource optimization in FPGA using genetic algorithm. IJCA 17(2):95–101
Sangiovanni-Vincentelli A, El Gamal A, Rose J (1993) Synthesis methods for field programmable gate arrays. Proc IEEE 81(7):1057–1083
French M, Wang L, Anderson T, Wirthlin M (2005) Post synthesis level power modeling of FPGAs. In: Proceedings of the 13th annual IEEE symposium on field-programmable custom computing machines (FCCM’05), IEEE, Washington
Cassel M, Kastensmidt FL (2006) Evaluating one-hot encoding finite state machines for SEU reliability in SRAM-based FPGAs. In: Proceedings of the 12th IEEE international on-line testing, Symposium (IOLTS’06). IEEE, Washington, pp 145–150
Ferrandi F, Lanzi PL, Palermo G, Pilato C, Sciuto D, Tumeo A, Politecnico di Milano (2007) An evolutionary approach to area-time optimization of FPGA designs, IEEE
St anislaw Deni ziak, Mar iu s z WiGniews ki (2009) A symbolic RTL synthesis for LUT—based FPGAs, IEEE
Cong J, Liu B, Neuendorffer S, Noguera J, Vissers K, Zhang Z (2011) High Level Synthesis for FPGAs: from prototyping to deployment. IEEE Trans Comput Aided Design Int Circuits Sys 30(4):473–491
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer Science+Business Media New York
About this paper
Cite this paper
Uma, R., Dhavachelvan, P. (2013). Performance Enhancement Through Optimization in FPGA Synthesis: Constraint Specific Approach. In: Chaki, N., Meghanathan, N., Nagamalai, D. (eds) Computer Networks & Communications (NetCom). Lecture Notes in Electrical Engineering, vol 131. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-6154-8_19
Download citation
DOI: https://doi.org/10.1007/978-1-4614-6154-8_19
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-6153-1
Online ISBN: 978-1-4614-6154-8
eBook Packages: EngineeringEngineering (R0)