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A New Low Voltage Low Power Consumption Comparator for Successive Approximation Register ADCs

Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 202)

Abstract

A New low-voltage low-power comparator for Successive-Approximation Register Analog-to-Digital Converter (ADC) has been designed. The input is amplified by a differential amplifier with positive feedback structure in the pre-amplifier. The positive feedback latch can reduce the power consumption. Using a constant bias circuit to provide two different bias voltages, an eliminated effect of different process variations on the amplifier is observed. All cells of the dynamic comparator have been simulated in a 0.13um CMOS technology process by Cadence tools. The total size of this dynamic comparator is less than 0.02 mm2.

Keywords

Analog-to-digital converter Preamplifiers Latches 

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Copyright information

© Springer Science+Business Media New York 2012

Authors and Affiliations

  1. 1.School of Communication and Information EngineeringUniversity of Electronic Science and Technology of ChinaChengduChina

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