Abstract
This chapter first illustrates the overall envisioned algorithm-architecture co-design flow for the proposed Domain Specific Instruction set Processor (DSIP) architecture template. Then, a part of this overall flow, i.e. the architecture template instantiation design flow, is explained. The proposed instantiation design flow can significantly contribute in bridging the cultural gap between algorithm and architecture designers, which is very essential for meeting the requirements of future designs. To demonstrate the feasibility of the proposed design flow, the application on two case studies is shown. This chapter complements the proposed DSIP architecture template of this book. Section 7.1 motivates the need for an algorithm-architecture co-design flow and reviews related issues. The proposed architecture template instantiation design flow is introduced in Sect. 7.2. In Sect. 7.3 the proposed design flow is applied to obtain the architecture instance for case study 1, i.e. the Multiple Input Multiple Output (MIMO) detector. The design of the Finite Impulse Response (FIR) filter architecture instances, i.e. case study 2, is shown in Sect. 7.4. Finally, Sect. 7.5 concludes this chapter.
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Fasthuber, R., Catthoor, F., Raghavan, P., Naessens, F. (2013). Front-End Design Flow: Bridging the Algorithm-Architecture Gap. In: Energy-Efficient Communication Processors. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4992-8_7
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DOI: https://doi.org/10.1007/978-1-4614-4992-8_7
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