Abstract
This chapter demonstrates the high energy efficiency of the proposed Domain Specific Instruction set Processor (DSIP) architecture template concept (see Chap. 3) on a challenging very high throughput and low latency Fast Fourier Transformation (FFT) processing architecture instance for both Wireless Local Area Network (WLAN) and 60 GHz applications. We implement the hardware and software of this design by utilizing the commercial Target processor design tool suite. The resulting design meets the demanding requirements and is more efficient than comparable state-of-the-art solutions. Section 6.1 motivates this case study and summarizes related work. The flexibility requirements for WLAN and 60 GHz applications are explained in Sect. 6.2. In Sect. 6.3, the algorithm choice and the algorithm properties are explained. The proposed DSIP architecture instance is presented in Sect. 6.4. Software mapping and hardware implementation results are given in Sect. 6.5. Section 6.6 compares the results to Application Specific Integrated Circuit (ASIC) and processor implementations from literature. Finally, Sect. 6.7 concludes this chapter.
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References
Atak, O., Atalar, A., Arikan, E., Ishebabi, H., Kammler, D., Ascheid, G., Meyr, H., Nicola, M., Masera, G.: Design of application specific processors for the cached FFT algorithm. In: IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), vol. 3, pp. III-III (2006). doi:10.1109/ICASSP.2006.1660832
Baas, B.: A generalized cached-FFT algorithm. In: IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), vol. 5, pp. 89–92. IEEE (2005). doi:10.1109/ICASSP.2005.1416247
Baykas, T., Sum, C.S., Lan, Z., Wang, J., Rahman, M., Harada, H., Kato, S.: IEEE 802.15.3c: the first IEEE wireless standard for data rates over 1 Gb/s. IEEE Commun. Mag. 49(7), 114–121 (2011). doi:10.1109/MCOM.2011.5936164
Beheshti, B.: On performance of LTE UE DFT and FFT implementations in flexible software based baseband processors. In: IEEE Long Island Systems, Applications and Technology conference (LISAT), pp. 1–4 (2009). doi:10.1109/LISAT.2009.5031556
van Berkel, C.: Multi-core for mobile phones. In: Design, Automation and Test in Europe (DATE), pp. 1260–1265 (2009)
Bo, Y., Han, J., Zou, Y., Zeng, X.: A low power ASIP for precision configurable FFT processing. In: Asia-Pacific Signal Information Processing Association Annual Summit and Conference (APSIPA ASC), pp. 1–4 (2012)
Cho, T., Lee, H.: A High-speed low-complexity modified FFT processor for high rate WPAN applications. IEEE Trans Very Large Scale Integr. Syst. 21(1), 187–191 (2013). doi:10.1109/TVLSI.2011.2182068
Cupaiuolo, T., Lo Iacono, D.: A flexible and fast software implementation of the FFT on the BPE platform. In: Design, Automation and Test in Europe (DATE), pp. 1467–1470 (2012). doi:10.1109/DATE.2012.6176598
Fasthuber, R., Li, M., Novo, D., Raghavan, P., Van der Perre, L., Catthoor, F.: Energy-efficient run-time scalable soft-output SSFE MIMO detector architectures. In: Transaction on High-Performance Embedded Architectures and Compilers (HiPEAC), Special Issue SAMOS 2009, vol. 5, no. 3, pp. 1–20 (2011)
Guan, X., Fei, Y., Lin, H.: Hierarchical design of an application-specific instruction set processor for high-throughput and scalable FFT processing. IEEE Trans on Very Large Scale Integr. Syst. 20(3), 551–563 (2012). doi:10.1109/TVLSI.2011.2105512
Heo, K., Cho, S., Lee, J., Sunwoo, M.: Application-specific DSP architecture for fast Fourier transform. In: IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), pp. 369–377 (2003). doi:10.1109/ASAP.2003.1212860
Huang, S.J., Chen, S.G.: A green FFT processor with 2.5-GS/s for IEEE 802.15.3c (WPANs). In: International Conference on Green Circuits and Systems (ICGCS), pp. 9–13 (2010). doi:10.1109/ICGCS.2010.5543105
Huang, S.J., Chen, S.G.: A high-throughput Radix-16 FFT processor with parallel and normal input/output ordering for IEEE 802.15.3c Systems. IEEE Trans. Circuits Syst. 59(8), 1752–1765 (2012). doi:10.1109/TCSI.2011.2180430
Janhunen, J., Pitkanen, T., Silven, O., Juntti, M.: Fixed- and floating-point processor comparison for MIMO-OFDM detector. IEEE J. Sel. Top. Signal Process. 5(8), 1588–1598 (2011). doi:10.1109/JSTSP.2011.2165830
Jayapala, M., Barat, F., Catthoor, F., Corporaal, H., Deconinck, G.: Clustered loop buffer organization for low energy VLIW embedded processors. IEEE Trans. Comput. 54(6), 672–683 (2005)
Jayasumana, G., Loeffler, C.: Searching for the best Cooley-Tukey FFT algorithms. In: IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), vol. 12, pp. 2408–2411 (1987). doi:10.1109/ICASSP.1987.1169923
Liu, G., Feng, Q.: ASIC design of low-power reconfigurable FFT processor. In: International Conference on ASIC (ASICON), pp. 44–47 (2007). doi:10.1109/ICASIC.2007.4415563
Perahia, E., Cordeiro, C., Park, M., Yang, L.L.: IEEE 802.11ad: defining the next generation multi-Gbps Wi-Fi. In: IEEE Consumer Communications and Networking Conference (CCNC), pp. 1–5 (2010). doi:10.1109/CCNC.2010.5421713
Raghavan, P., Lambrechts, A., Jayapala, M., Catthoor, F., Verkest, D., Corporaal, H.: Very wide register: an asymmetric register file organization for low power embedded processors. In: Design, Automation and Test in Europe (DATE). IMEC (2007)
Rowen, C., Nuth, P., Fiske, S.: A DSP architecture optimized for wireless baseband. In: International Symposium on System-on-Chip (SOC), pp. 151–156 (2009). doi:10.1109/SOCC.2009.5335658
Tang, S.N., Liao, C.H., Chang, T.Y.: An Area- and energy-efficient multimode FFT processor for WPAN/WLAN/WMAN systems. IEEE J. Solid-State Circuits 47(6), 1419–1435 (2012). doi:10.1109/JSSC.2012.2187406
Target ASIP development toolsuite (inc. IP Designer, IP Programmer), Target Compiler Technologies. http://www.retarget.com/
Zainal, M., Yoshizawa, S., Miyanaga, Y.: Low power FFT design for wireless communication systems. In: International Symposium on Intelligent Signal Processing and Communications Systems (ISPACS), pp. 1–4 (2008). doi:10.1109/ISPACS.2009.4806724
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Fasthuber, R., Catthoor, F., Raghavan, P., Naessens, F. (2013). Case Study 3: DSIP Architecture Instance for FFT Computation. In: Energy-Efficient Communication Processors. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4992-8_6
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DOI: https://doi.org/10.1007/978-1-4614-4992-8_6
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