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Background and Related Work

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Energy-Efficient Communication Processors

Abstract

In this chapter, first important background information and then an overview of the main related work are provided. The intention of this chapter is to present the reader a good overview of the context of this book topic. Considering the broad range of related disciplines, an exhaustive state-of-the-art survey of all related literature is outside the scope. However we have done our best to ensure that everything which is sufficiently close to the topic of this book is summarized. More references, especially for direct benchmarks, are provided in the chapters that follow. Section 2.1 provides background information on the functionality of wireless communication systems. Suitable architecture styles for the implementation of wireless communication systems are reviewed in Sect. 2.2. An overview of the general system design flow, which leads to the implementation of the physical layer functionality, is provided in Sect. 2.3. In the Sect. 2.4–2.7, related work on design methodologies is reviewed. Related work on architectures and templates is reviewed in Sect. 2.8. Section 2.9 summarizes and concludes this chapter.

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References

  1. Abdelall, M., Shalash, A.F., Fahmy, H.A.H.: A reconfigurable baseband processor for wireless OFDM synchronization sub-system. In: IEEE International Symposium on Circuits and System (ISCAS), pp. 2385–2388. IEEE (2011). doi:10.1109/ISCAS.2011.5938083

  2. Absar, J., Lambrechts, A., Min, L., Jayapala, M., Raghavan, P., Vandecappelle, A.: Locality optimization in wireless applications. In: International Conference on Hardware/Software Codesign and System, Synthesis (CODES+ISSS), pp. 125–130 (2007)

    Google Scholar 

  3. Agrawal, P., Fasthuber, R., Raghavan, P., Van der Aa, T., Ahmad, U., Van der Perre, L., Catthoor, F.: High level analysis of trade-offs across different partitioning schemes for wireless applications. In: IEEE Workshop on Signal Processing System (SIPS) (2011)

    Google Scholar 

  4. Agrawal, P., Raghavan, P., Hartmann, M., Sharma, N., Van der Perre, L., Catthoor, F.: Early exploration for platform architecture instantiation with multi-mode application partitioning. In: Design Automation Conference (DAC) (2013)

    Google Scholar 

  5. Agrawal, P., Sugand, K., Palkovic, M., Raghavan, P., Van der Perre, L., Catthoor, F.: Partitioning and assignment exploration for multiple modes of IEEE 802.11n modem on heterogeneous MPSoC platform. In: Euromicro Conference on Digital System Design (DSD), pp. 608–615 (2012). doi:10.1109/DSD.2012.102

  6. Airoldi, R., Garzia, F., Anjum, O., Nurmi, J.: Homogeneous MPSoC as baseband signal processing engine for OFDM systems. In: International Symposium on System on Chip (ISSOC), pp. 26–30 (2010). doi:10.1109/ISSOC.2010.5625562

  7. Alomary, A., Nakata, T., Honma, Y., Sato, J., Hikichi, N., Imai, M.: PEAS-I: A hardware/software co-design system for ASIPs. In: European Design Automation Conference (EURO-DAC), pp. 2–7 (1993). doi:10.1109/EURDAC.1993.410608

  8. Liberate, Altos Design Automation. http://www.altos-da.com/

  9. Anjum, O., Ahonen, T., Garzia, F., Nurmi, J., Brunelli, C., Berg, H.: State of the art baseband DSP platforms for Software Defined Radio: a survey. EURASIP J. Wirel. Commun. Networking 2011(1), 5 (2011). doi:10.1186/1687-1499-2011-5

  10. Artes, A., Huisken, J., Ayala Rodrigo, J.L., Fasthuber, R., Catthoor, F.: Energy impact of loop buffer schemes used in embedded systems. IEEE Embedded System Letters (ESL) (Submitted, 2012)

    Google Scholar 

  11. Ashkar, M.: Integrate custom layout with ASIC back-end design flow for high performance datapath design. In: International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), pp. 1901–1904 (2008). doi:10.1109/ICSICT.2008.4734931

  12. ASIP Solutions, Inc.: ASIP Meister. URL http://www.asip-solutions.com/

  13. Auger, F., Lou, Z., Feuvrie, B., Li, F.: Multiplier-free divide, square root, and log algorithms [DSP Tips and Tricks]. IEEE Signal Process. Mag. 28(4), 122–126 (2011). doi:10.1109/MSP.2011.941101

    Google Scholar 

  14. Badaroglu, M., Desset, C., Ryckaert, J., De Heyn, V., Der Plas, G., Wambacq, P., Van Poucke, B.: Analog-digital partitioning for low-power UWB impulse radios under CMOS scaling. EURASIP J. Wirel. Commun. Networking pp. 1–8 (2006). doi:10.1155/WCN/2006/72430

  15. Balfour, J., Dally, W.J., Black-Schaffer, D., Parikh, V., Park, J.: An energy-efficient processor architecture for embedded systems. Comput. Archit. Lett. 7(1), 29–32 (2007)

    Article  Google Scholar 

  16. Banakar, R., Steinke, S., Balakrishnan, M., Marwedel, P.: Scratchpad memory: a design alternative for cache on-chip memory in embedded systems. In: International Symposium on Hardware/Software Codesign (CODES), pp. 73–78. ACM Press (2002). doi:10.1109/CODES.2002.1003604

  17. Baruah, S.: Task partitioning upon heterogeneous multiprocessor platforms. In: IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 536–543 (2004). doi:10.1109/RTTAS.2004.1317301

  18. Bekiaris, D., Papanikolaou, A., Stamelos, G., Soudris, D., Economakos, G., Pekmestzi, K.: A standard-cell library suite for deep-deep sub-micron CMOS technologies. In: International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), pp. 1–6 (2011). doi:10.1109/DTIS.2011.5941445

  19. van Berkel, C.: Multi-core for mobile phones. In: Design, Automation and Test in Europe (DATE), pp. 1260–1265 (2009)

    Google Scholar 

  20. van Berkel, K., Heinle, F., Meuwissen, P.P.E., Moerman, K., Weiss, M.: Vector processing as an enabler for software-defined radio in handheld devices. J. Adv. Signal Process. (EURASIP) 2005(16), 2613–2625 (2005). doi:10.1155/ASP.2005.2613

  21. Bernard, C., Clermidy, F.: A low-power VLIW processor for 3GPP-LTE complex numbers processing. In: Design, Automation and Test in Europe (DATE), pp. 1–6 (2011)

    Google Scholar 

  22. Berset, T., Catthoor, F.: Technical note TN-11-WATS-TIP2: high level estimation for independent component analysis. Technical report, Holst Centre, IMEC-NL (2012)

    Google Scholar 

  23. Beszédes, A., Ferenc, R., Gyimóthy, T., Dolenc, A., Karsisto, K.: Survey of code-size reduction methods. ACM Comput. Surv. 35(3), 223–267 (2003). doi:10.1145/937503.937504

    Google Scholar 

  24. Bhagawat, P., Dash, R., Choi, G.: Dynamically reconfigurable soft output MIMO detector. In: International Conference on Computer Design (ICCD), pp. 68–73 (2008). doi:10.1109/ICCD.2008.4751842

  25. Bhagawat, P., Dash, R., Choi, G.: Array like runtime reconfigurable MIMO detectors for 802.11n WLAN: a design case study. In: Asia and South Pacific Design Automation Conference (DAC-ASP), pp. 751–756 (2009). doi:10.1109/ASPDAC.2009.4796570

  26. Bougard, B., De Sutter, B., Rabou, S., Novo, D., Allam, O., Dupont, S., Van der Perre, L.: A coarse-grained array based baseband processor for 100Mbps+ software defined radio. In: Design, Automation and Test in Europe (DATE), pp. 716–721. IMEC (2008). doi:10.1109/DATE.2008.4484763

  27. Cadence, C-to-Silicon. http://www.cadence.com/

  28. Cadence, Encounter Digital Implementation System. http://www.cadence.com/

  29. Cadence, Encounter Power System. http://www.cadence.com/

  30. Cadence, Encounter RTL Compiler. http://www.cadence.com/

  31. Cadence, Encounter Timing System. http://www.cadence.com/

  32. Cadence, Physical Verification System. http://www.cadence.com/

  33. Cadence, Virtuoso Analog Design Environment. http://www.cadence.com/

  34. Cadence, Virtuoso Layout Suite. http://www.cadence.com/

  35. Catthoor, F.: Slide set that explains the high-level estimation flow, IMEC. Available on request

    Google Scholar 

  36. Catthoor, F., Danckaert, K., Kulkarni, K., Brockmeyer, E., Kjeldsberg, P.G., van Achteren, T., Omnes, T.: Data Access and Storage Management for Embedded Programmable Processors. Springer (2010)

    Google Scholar 

  37. Catthoor, F., Danckaert, K., Wuytack, S., Dutt, N.: Code transformations for data transfer and storage exploration preprocessing in multimedia processors. IEEE Des. Test Comput. 18(3), 70–82 (2001)

    Article  Google Scholar 

  38. Catthoor, F., Raghavan, P., Lambrechts, A., Jayapala, M., Kritikakou, A., Absar, J.: Ultra-Low Energy Domain-Specific Instruction-Set Processors, 1st edn. Springer (2010)

    Google Scholar 

  39. Catthoor, F., Wuytack, S., de Greef, G., Banica, F., Nachtergaele, L., Vandecappelle, A.: Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design. Springer (1998)

    Google Scholar 

  40. Cerato, B., Viterbo, E.: Hardware implementation of a low-complexity detector for large MIMO. In: IEEE International Symposium on Circuits and System (ISCAS), pp. 593–596 (2009). doi:10.1109/ISCAS.2009.5117818

  41. CEVA Inc.: CEVA DSP core X1641 Product Note (2008). http://www.ceva-dsp.com/

  42. CEVA Inc.: CEVA-XC321 Product Note (2009). http://www.ceva-dsp.com/

  43. Chandra, A.: Spectrum management for future generation wireless based technology. In: European Wireless Technology Conference (EuWIT), pp. 201–205 (2009)

    Google Scholar 

  44. Changqi, Y., Xianlong, H., Yici, C., Wenting, H., Tong, J., Weimin, W.: Standard-cell based data-path placement utilizing regularity. In: International Conference on ASIC (ICASIC), pp. 97–100 vol. 1 (2003). doi:10.1109/ICASIC.2003.1277499

  45. Chen, I., Chun, A., Tsui, E., Honary, H., Tsai, V.: Overview of intels reconfigurable communication architecture. In: Workshop on Application Specific Processor, vol. 3, pp. 95–102. Intel (2004)

    Google Scholar 

  46. Chen, K.C.: A green software-defined communication processor for dynamic spectrum access. In: IEEE International Symposium on Personal, Indoor and Mobile Radio Communication (PIMRC), pp. 774–779 (2010). doi:10.1109/PIMRC.2010.5671956

  47. Chien-Jen, H., Chung-Wen, Y., Hsi-Pin, M.: A power-efficient configurable low-complexity MIMO detector. IEEE Trans. Circuits and Syst. 56(2), 485–496 (2009). doi:10.1109/TCSI.2008.2001368

    Google Scholar 

  48. Chinnery, D., Keutzer, K.: Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low Power Design. Springer (2007)

    Google Scholar 

  49. Chun, A., Tsui, E., Chen, I., Honary, H., Lin, J.: Application of the intel reconfigurable communications architecture to 802.11a, 3G and 4G standards. In: Proceedings of the 6th Circuits and Systems Symposium on Emerging Technologies (CASSET), vol. 2, pp. 659–662. Intel (2004)

    Google Scholar 

  50. Cichon, G., Robelly, P., Seidel, H., Matus, E., Bronzel, M., Fettweis, G.: Synchronous Transfer Architecture (STA). In: Lecture Notes in Computer Science. Mobile Communcations Chair, TU-Dresden, pp. 193–207. Springer (2004). doi:10.1007/978-3-540-27776-7_36

    Google Scholar 

  51. Clermidy, F., Bernard, C., Lemaire, R., Martin, J., Miro-Panades, I., Thonnart, Y., Vivet, P., Wehn, N.: A 477mW NoC-based digital baseband for MIMO 4G SDR. In: IEEE International Solid-State Circuits Conference (ISSCC), pp. 278–279 (2010). doi:10.1109/ISSCC.2010.5433920

  52. Clermidy, F., Bernard, C., Lemaire, R., Martin, J., Miro-Panades, I., Thonnart, Y., Vivet, P., Wehn, N.: MAGALI: a network-on-chip based multi-core system-on-chip for MIMO 4G SDR. In: International Conference on Integrated Circuit Design and Technology (ICICDT), pp. 74–77 (2010). doi:10.1109/ICICDT.2010.5510291

  53. Cong, J., Gururaj, K., Han, G., Kaplan, A., Naik, M., Reinman, G.: MC-Sim: an efficient simulation tool for MPSoC designs. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 364–371 (2008). doi:10.1109/ICCAD.2008.4681599

  54. Cong, J., Sarkar, V., Reinman, G., Bui, A.: Customizable domain-specific computing. IEEE Des. Test Comput. 28(2), 6–15 (2011). doi:10.1109/MDT.2010.141

    Google Scholar 

  55. Corporaal, H.: Microprocessor Architectures: From VLIW to TTA. Wiley (1998)

    Google Scholar 

  56. Coussy, P., Gajski, D.D., Meredith, M., Takach, A.: An introduction to high-level synthesis. IEEE Des. Test Comput. 26(4), 8–17 (2009). doi:10.1109/MDT.2009.69

  57. Coussy, P., Morawiec, A.: High-Level Synthesis from Algorithm to Digital Circuit, 1 edn. Springer, Dordrecht (2008)

    Google Scholar 

  58. Cupaiuolo, T., Siti, M., Tomasoni, A.: Low-complexity high throughput VLSI architecture of soft-output ML MIMO detector. In: Design, Automation and Test in Europe (DATE), pp. 1396–1401 (2010)

    Google Scholar 

  59. Danckaert, K., Catthoor, F., De Man, H.: Platform independent data transfer and storage exploration illustrated on a parallel cavity detection algorithm. In: Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), pp. 1669–1675 (1999)

    Google Scholar 

  60. Das, S., Khatri, S.: An efficient and regular routing methodology for datapath designs using net regularity extraction. IEEE Trans. Comput. Aided Des. 21(1), 93–101 (2002). doi:10.1109/43.974141

    Google Scholar 

  61. De Micheli, G.: Logic synthesis and physical design: Quo vadis? In: Design, Automation and Test in Europe (DATE), pp. 1–1. EPFL (2011)

    Google Scholar 

  62. Dejonghe, A.: R &D fact sheet: digital solutions for cognitive Radio. Technical report, IMEC (2010)

    Google Scholar 

  63. Derudder, V., Bougard, B., Couvreur, A., Dewilde, A., Dupont, S., Folens, L., Hollevoet, L., Naessens, F., Novo, D., Raghavan, P., Schuster, T., Stinkens, K., Weijers, J.W., Van der Perre, L.: A 200Mbps + 2.14nJ/b digital baseband multi processor system-on-chip for SDRs. In: Symposium on VLSI Circuits, pp. 292–293 (2009)

    Google Scholar 

  64. Eleyan, N.N., Ken, L., Kamal, M., Mohammed, B., Bassett, P.: Semi-custom design flow: leveraging place and route tools in custom circuit design. In: IEEE IC Design and Technology (ICICDT), pp. 143–147. Qualcomm, DSP core design (2009)

    Google Scholar 

  65. Falk, H., Marwedel, P.: Source Code Optimization Techniques for Data Flow Dominated Embedded Software. Springer (2004)

    Google Scholar 

  66. Fasthuber, R., Li, M., Novo, D., Raghavan, P., Van der Perre, L., Catthoor, F.: Energy-efficient run-time scalable soft-output SSFE MIMO detector architectures. In: Transaction on High-Performance Embedded Architectures and Compilers (HiPEAC), Special Issue SAMOS 2009, vol. 5, no. 3, pp. 1–20 (2011)

    Google Scholar 

  67. Fasthuber, R., Li, M., Novo, D., Van Der Perre, L., Catthoor, F.: Novel energy-efficient scalable soft-output SSFE MIMO detector architectures. In: International Conference on Embedded Computer Systems (IC-SAMOS). IMEC (2009). doi:10.1109/ICSAMOS.2009.5289228

  68. Fasthuber, R., Li, M., Novo, D., Van Der Perre, L., Catthoor, F.: Exploration of soft-output MIMO detector implementations on massive parallel processors. J. Signal Process. Syst. 64(1), 75–92 (2010). doi:10.1007/s11265-010-0499-0

    Google Scholar 

  69. Fauth, A., Van Praet, J., Freericks, M.: Describing instruction set processors using nML. In: Design, Automation and Test in Europe (DATE), pp. 503–507 (1995). doi:10.1109/EDTC.1995.470354

  70. Freescale Semiconductor Inc.: Star Core MSC8158 Product Brief, Review (2010). http://www.freescale.com/

  71. Freescale Semiconductor Inc.: Star Core MSC8256 Data Sheet, Rev. 1(2010). http://www.freescale.com/

  72. Fridman, J., Greenfield, Z.: The TigerSHARC DSP architecture. IEEE Micro 20(1), 66–76 (2000). doi:10.1109/40.820055

    Google Scholar 

  73. Ganesan, S., Vemuri, R.: Analog-digital partitioning for field-programmable mixed signal systems. In: Conference on Advanced Research in VLSI (ARVLSI), pp. 172–185 (2001). doi:10.1109/ARVLSI.2001.915559

  74. Gangwar, A., Balakrishnan, M., Kumar, A.: Impact of inter-cluster communication mechanisms on ILP in clustered VLIW architectures. ACM Trans. Des. Autom. Electron. Syst. 12(1) (2007)

    Google Scholar 

  75. Gansen, M., Richter, F., Weiss, O., Noll, T.: A datapath generator for full-custom macros of iterative logic arrays. In: IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), pp. 438–447 (1997). doi:10.1109/ASAP.1997.606849

  76. Glossner, J., Chirca, K., Schulte, M., Wang, H., Nasimzada, N., Har, D., Wang, S., Hoane, J.A., Nacer, G., Moudgill, M., Vassiliadis, S.: Sandblaster Low Power DSP. In: IEEE Custom Integration Circuits Conference (CICC), pp. 575–581. Sandbridge Technologies, Delft University of Technologies, University of Wisconsin (2004)

    Google Scholar 

  77. Gonzalez, R.: Xtensa: a configurable and extensible processor. IEEE Micro 20(2), 60–70 (2000). doi:10.1109/40.848473

    Google Scholar 

  78. Gordon-Ross, A., Vahid, F.: Dynamic loop caching meets preloaded loop caching-a hybrid approach. In: IEEE International Conference on Computer Design (ICCD), pp. 446–449 (2002). doi:10.1109/ICCD.2002.1106810

  79. Guan, X., Fei, Y., Lin, H.: A hierarchical design of an application-specific instruction set processor for high-throughput FFT. IEEE International Symposium on Circuits and System (ISCAS) (2009)

    Google Scholar 

  80. Halambi, A., Grun, P., Ganesh, V., Khare, A., Dutt, N., Nicolau, A.: EXPRESSION: a language for architecture exploration through compiler/simulator retargetability. In: Design, Automation and Test in Europe (DATE), pp. 485–490 (1999). doi:10.1109/DATE.1999.761170

  81. Heyrman, K.: Control of sectioned on-chip communication. Ph.D. thesis, University of Gent, Belgium (2009)

    Google Scholar 

  82. Heysters, P.M., Smit, G.J.M.: Mapping of DSP algorithms on the MONTIUM architecture. In: International Parallel and Distributed Processing Symposium (IPDPS). University of Twente (Netherlands) (2003)

    Google Scholar 

  83. Ienne, P., Leupers, R.: Customizable Embedded Processors: Design Technologies and Applications. Morgan Kaufmann (2006)

    Google Scholar 

  84. Imai, M., Takeuchi, Y., Ohtsuki, N., Hikichi, N.: Compiler generation techniques for embedded processors and their application to HW/SW codesign. System-level, synthesis pp. 293–320 (1999)

    Google Scholar 

  85. Inc., M.M.: DataPath compiler datasheet (2006). http://www.micromagic.com/

  86. Itoh, M., Higaki, S., Sato, J., Shiomi, A., Takeuchi, Y., Kitajima, A., Imai, M.: PEAS-III: an ASIP design environment. In: International Conference on Computer Design (ICCD), pp. 430–436 (2000). doi:10.1109/ICCD.2000.878319

  87. ROCCC, Jacquard Computing. http://www.jacquardcomputing.com/roccc/

  88. Jalier, C., Lattard, D., Sassatelli, G., Benoit, P., Torres, L.: A homogeneous MPSoC with dynamic task mapping for software defined radio. In: IEEE Computer Society Symposium on VLSI (ISVLSI), pp. 345–350 (2010). doi:10.1109/ISVLSI.2010.110

  89. Janhunen, J., Pitkanen, T., Silven, O., Juntti, M.: Fixed- and floating-point processor comparison for MIMO-OFDM detector. IEEE J. Sel. Top. Signal Process. 5(8), 1588–1598 (2011). doi:10.1109/JSTSP.2011.2165830

    Google Scholar 

  90. Jayapala, M., Barat, F., Catthoor, F., Corporaal, H., Deconinck, G.: Clustered loop buffer organization for low energy VLIW embedded processors. IEEE Trans. Comput. 54(6), 672–683 (2005)

    Article  Google Scholar 

  91. Kandemir, M., Kadayif, I., Choudhary, A., Ramanujam, J., Kolcu, I.: Compiler-directed scratch pad memory optimization for embedded multiprocessors. IEEE Trans. Very Large Scale Integr. VLSI Syst. 12(3), 281–287 (2004). doi:10.1109/TVLSI.2004.824299

    Google Scholar 

  92. Kapasi, U., Rixner, S., Dally, W., Khailany, B., Mattson, P., Owens, J.: Programmable stream processors. Computer 36(8), 54–62 (2003). doi:10.1109/MC.2003.1220582

    Google Scholar 

  93. Karlstrom, P., Zhou, W., Wang, C.h., Liu, D.: Design of PIONEER: A case study using NoGap. In: Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), pp. 53–56 (2010). doi:10.1109/PRIMEASIA.2010.5604962

  94. Kavvadias, N., Nikolaidis, S.: Zero-overhead loop controller that implements multimedia algorithms. IEEE Proc. Comput. Digital Tech. 152(4), 517 (2005). doi:10.1049/ip-cdt:20041187

    Google Scholar 

  95. Keutzer, K., Malik, S., Newton, A.: From ASIC to ASIP: the next design discontinuity. In: IEEE International Conference on Computer Design (ICCD), pp. 84–90 (2002). doi:10.1109/ICCD.2002.1106752

  96. Kim, E.P., Shanbhag, N.R.: An energy-efficient multiple-input multiple-output (MIMO) detector architecture. In: IEEE Workshop on Signal Processing System (SIPS), pp. 239–244 (2011). doi:10.1109/SiPS.2011.6088981

  97. Kim, T.H., Park, I.C.: Small-area and low-energy K-best MIMO detector using relaxed tree expansion and early forwarding. IEEE Trans. Circuits Syst. 57(10), 2753–2761 (2010). doi:10.1109/TCSI.2010.2046249

  98. Kin, J., Gupta, M., Mangione-Smith, W.: Filtering memory references to increase energy efficiency. IEEE Trans. Comput. 49(1), 1–15 (2000). doi:10.1109/12.822560

    Google Scholar 

  99. Knagge, G., Bickerstaff, M., Ninness, B., Weller, S.R., Woodward, G.: A VLSI 8x8 MIMO Near-ML decoder engine. In: IEEE Workshop on Signal Processing System (SIPS), pp. 387–392 (2006). doi:10.1109/SIPS.2006.352614

  100. Kneip, J., Weiss, M., Drescher, W., Aue, V., Strobel, J., Oberthuer, T., Bolle, M., Fettweis, G.: Single chip programmable baseband ASSP for 5 GHz wireless LAN applications. IECICE Trans. Electron. E85-C(2), 359–367 (2002)

    Google Scholar 

  101. Knowles, S.: The SOC future is soft. In: IEEE Cambridge Branch Seminar (2005)

    Google Scholar 

  102. Kogel, T., Leupers, R., Meyr, H.: Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms. Springer (2006)

    Google Scholar 

  103. Kokkeler, A.B.J.: Analog-digital codesign using coarse quantization. Ph.D. thesis, University of Twente, Enschede, The Netherlands (2005)

    Google Scholar 

  104. Kozyrakis, C., Patterson, D.: Scalable vector processors for embedded systems. IEEE Micro 23(6), 36–45 (2003). doi:10.1109/MM.2003.1261385

    Google Scholar 

  105. Kunze, S., Matus, E., Fettweis, G.: ASIP decoder architecture for convolutional and LDPC codes. In: IEEE International Symposium on Circuits and System (ISCAS), i, pp. 2457–2460 (2009). doi:10.1109/ISCAS.2009.5118298

  106. Lapinskii, V., Jacome, M., de Veciana, G.: Application-specific clustered VLIW datapaths: early exploration on a parameterized design space. IEEE Trans. Comput. Aided Des. 21(8), 889–903 (2002). doi:10.1109/TCAD.2002.800451

    Google Scholar 

  107. Lee, H., Chakrabarti, C., Mudge, T.: A low-power DSP for wireless communications. IEEE Trans. Very Large Scale Integr. Syst. 18(9), 1310–1322 (2010)

    Google Scholar 

  108. Leroy, A., Milojevic, D., Verkest, D., Robert, F., Catthoor, F.: Concepts and implementation of spatial division multiplexing for guaranteed throughput in networks-on-chip. IEEE Trans. Comput. 57(9), 1182–1195 (2008). doi:10.1109/TC.2008.82

    Google Scholar 

  109. Leupers, R., Marwedel, P.: Retargetable code generation based on structural processor descriptions. In: Design Automation for Embedded Systems, pp. 1–36. Kluwer Academic Publishers (1998)

    Google Scholar 

  110. Li, L., Shi, M.: Software-hardware partitioning strategy using hybrid genetic and Tabu search. In: International Conference on Computer Science and Software Engineering (CSSE), pp. 83–86 (2008). doi:10.1109/CSSE.2008.488

  111. Li, M.: Algorithm and architecture co-design for software defined radio baseband. Ph.D. thesis, KU Leuven (2010)

    Google Scholar 

  112. Li, M., Amin, A., Appeltans, R., Torrea, R., Cappelle, H., Fasthuber, R., Dejonghe, A., Van der Perre, L.: Instruction set support and algorithm-architecture for fully parallel multi-standard soft-output demapping on baseband processors. In: IEEE Workshop on Signal Processing System (SIPS), pp. 140–145. IMEC (2010). doi:10.1109/SIPS.2010.5624777

  113. Li, M., Appeltans, R., Amin, A., Torrea-Duran, R., Cappelle, H., Hartmann, M., Yomo, H., Kobayashi, K., Dejonghe, A., Van Der Perre, L.: Overview of a software defined downlink inner receiver for category-E LTE-advanced UE. In: IEEE International Conference on Communication (ICC), pp. 1–5 (2011). doi:10.1109/icc.2011.5963387

  114. Li, M., Fasthuber, R., Novo, D., Van Der Perre, L., Catthoor, F.: Algorithm-architecture co-design of soft-output ML MIMO detector for parallel application specific instruction set processors. In: Design, Automation and Test in Europe (DATE), pp. 1608–1613. IMEC (2009)

    Google Scholar 

  115. Li-ya, L., Peng, L.: Low power implementation of datapath using regularity. J. Zhejiang Univ. Sci. A 6(6), 596–600 (2005). doi:10.1007/BF02841771

    Google Scholar 

  116. Liao, C.H., Wang, T.P., Chiueh, T.D.: A 74.8 mW soft-output detector IC for 8 x 8 spatial-multiplexing MIMO communications. IEEE J. Solid-State Circuits 45(2), 411–421 (2010). doi:10.1109/JSSC.2009.2037292

    Google Scholar 

  117. Limberg, T., Winter, M., Bimberg, M., Klemm, R., Matus, E., Tavares, M.B., Fettweis, G., Ahlendorf, H., Robelly, P.: A fully programmable 40 GOPS SDR single chip baseband for LTE/WiMAX terminals. In: European Solid-State Circuits Conference (ESSCIRC), pp. 466–469. Technische Universtaet Dresden and Vodafone Chair Mobile Communications Systems (Fettweis) (2008)

    Google Scholar 

  118. Lin, Y., Lee, H., Woh, M., Harel, Y., Mahlke, S., Mudge, T.: SODA: A low-power architecture for software radio. In: International Symposium on Computer Architecture (ISCA), vol. 33, pp. 89–101. University of Michigan; Arizona State University, ARM Ltd., IEEE (2006). doi:10.1109/ISCA.2006.37

  119. Liu, D.: Embedded DSP Processor Design: Application Specific Instruction Set Processors. Morgan Kaufmann (2008)

    Google Scholar 

  120. Liu, L., Ye, F., Ma, X., Zhang, T., Ren, J.: A 1.1-Gb/s 115-pJ/bit configurable MIMO detector using 0.13um CMOS technology. IEEE Trans. Circuits Syst. 57(9), 701–705 (2010). doi:10.1109/TCSII.2010.2058494

    Google Scholar 

  121. Liu, T.H., Jiang, J.Y., Chu, Y.S.: A Low-Cost MMSE-SIC detector for the MIMO system: algorithm and hardware implementation. IEEE Trans. Circuits Syst. 58(1), 56–61 (2011). doi:10.1109/TCSII.2010.2092819

    Google Scholar 

  122. Lodi, A., Cappelli, A., Bocchi, M., Mucci, C., Innocenti, M., Bartolomeis, C.D., Ciccarelli, L., Giansante, R., Deledda, A., Campi, F., Toma, M., Guerrieri, R.: XiSystem: a XiRisc-based SoC with reconfigurable IO module. IEEE J. Solid-State Circuits 41(1), 85–96 (2006)

    Article  Google Scholar 

  123. Lu, W., Zhao, S., Zhou, X., Ren, J., Sobelman, G.: Reconfigurable baseband processing architecture for communication. IET Comput. Digit. Tech. 5(1), 63 (2011). doi:10.1049/iet-cdt.2009.0121

  124. Luo, D., Tsui, C.Y.: A hybrid algorithm and its re-configurable architecture for MIMO detector. In: IEEE International Midwest Symposium on Circuits and System (MWSCAS), pp. 297–300 (2009). doi:10.1109/MWSCAS.2009.5236095

  125. Magma, Hydra. http://www.magma-da.com/

  126. Magma, SiliconSmart. http://www.magma-da.com/

  127. Magma, Talus Design. http://www.magma-da.com/

  128. Magma, Titan Mixed-Signal Design Platform. http://www.magma-da.com/

  129. Mahdavi, M., Shabany, M.: Ultra high-throughput architectures for hard-output MIMO detectors in the complex domain. In: IEEE International Midwest Symposium on Circuits and System (MWSCAS), pp. 1–4 (2011). doi:10.1109/MWSCAS.2011.6026425

  130. Mansour, M., Shanbhag, N.: High-throughput LDPC decoders. IEEE Trans. Very Large Scale Integr. Syst. 11(6), 976–996 (2003). doi:10.1109/TVLSI.2003.817545

    Google Scholar 

  131. Marwedel, P.: Embedded System Design. Springer (2005)

    Google Scholar 

  132. Medra, A.: Semi-custom design to Reduce the interconnect energy in advanced technologies. Master thesis, Nile University, Egypt (2012)

    Google Scholar 

  133. Mei, B., Vernalde, S., Verkest, D., De Man, H., Lauwereins, R.: ADRES: an architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix. Lect. Notes Comput. Sci. 2778, 61–70 (2003)

    Article  Google Scholar 

  134. Catapult C, Mentor graphics. http://www.mentor.com/esl/catapult/overview

  135. Meyr, H.: System-on-chip for communications: the dawn of ASIPs and the dusk of ASICs. In: IEEE Workshop on Signal Processing Systems (SIPS), pp. 4–5 (2003). doi:10.1109/SIPS.2003.1235634

  136. Micheli, G.D., Benini, L.: Networks on Chips: Technology and Tools (Systems on Silicon). Morgan Kaufmann (2006)

    Google Scholar 

  137. ModelSim, Mentor Graphics. http://model.com/

  138. Moezzi-Madani, N., Thorolfsson, T., Chiang, P., Davis, W.R.: Area-efficient antenna-scalable MIMO detector for K-best sphere decoding. J. Signal Process. Syst. pp. 1–12 (2011). doi:10.1007/s11265-011-0595-9

  139. Mohammed, K., Mohamed, M.I.A., Daneshrad, B.: A Parameterized Programmable MIMO decoding architecture with a scalable instruction set and compiler. IEEE Trans. Very Large Scale Integr. Syst. 19(8), 1485–1489 (2011). doi:10.1109/TVLSI.2010.2049592

  140. Moudgill, M., Glossner, J., Agrawal, S., Nacer, G.: The Sandblaster 2.0 architecture and SB3500 implementation. In: SDR Forum. Sandbridge Technologies (2008)

    Google Scholar 

  141. Nilsson, A., Tell, E., Liu, D.: An 11 mm2, 70 mW fully programmable baseband processor for mobile WiMAX and DVB-T/H in 0.12um CMOS. IEEE J. Solid-State Circuits 44(1), 90–97 (2009). doi:10.1109/JSSC.2008.2007167

  142. Nofal, F.A., Nofal, M.R.: Top Down SoC Floor planning with ReUse. ChipEDA. EE Times, White paper (2008)

    Google Scholar 

  143. Novo, D.: Exploiting adaptive precision in software defined radios. Ph.D. thesis, KU Leuven (2010)

    Google Scholar 

  144. Nsenga, J.: Design of an air interface for 60 GHz multi-antenna systems and study of non-idealities impact on system performance. Ph.D. thesis, KU Leuven (2009)

    Google Scholar 

  145. Panda, P.R., Catthoor, F., Dutt, N.D., Danckaert, K., Brockmeyer, E., Kulkarni, C., Vandercappelle, A., Kjeldsberg, P.G.: Data and memory optimization techniques for embedded systems. ACM Trans. Des. Autom. Electron. Syst. 6(2), 149–206 (2001). doi:10.1145/375977.375978

  146. Papanikolaou, A.: Application-driven software configuration of communication networks and memory organizations. Ph.D. thesis, University of Gent, Belgium (2006)

    Google Scholar 

  147. Patel, D., Smolyakov, V., Shabany, M., Gulak, P.G.: VLSI implementation of a WiMAX/LTE compliant low-complexity high-throughput soft-output K-Best MIMO detector. In: IEEE International Symposium on Circuits and System (ISCAS), pp. 593–596 (2010). doi:10.1109/ISCAS.2010.5537524

  148. Picochip: PC205 Product Brief (2009). http://www.picochip.com/

  149. Portero, A., Carrabina, J., Catthoor, F.: HW/SW Implementation Trade-Offs of MPEG-4 Data-Flow Algorithm. LAP LAMBERT Academic Publishing (2010)

    Google Scholar 

  150. Potkonjak, M., Rabaey, J.: Optimizing resource utilization using transformations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(3), 277–292 (1994). doi:10.1109/43.265670

    Google Scholar 

  151. Pulley, D., Baines, R.: Software defined baseband processing for 3G base stations. In: International Conference on 3G Mobile Communication Technologies, vol. 4, pp. 123–127. Picochip (2003). doi:10.1049/cp:20030350

  152. Raab, W., Berthold, J., Hachmann, U., Langen, D., Schreiner, M.: Low power design of the X-GOLD SDR 20 baseband processor. In: Design, Automation and Test in Europe (DATE), pp. 792–793. Infineon Technologies AG, Germany and TU Dresden, Germany (2010)

    Google Scholar 

  153. Raghavan, P.: Low energy VLIW architecture extensions and compiler plug-ins for embedded systems. Ph.D. thesis, KU Leuven, IMEC (2009)

    Google Scholar 

  154. Raghavan, P., Lambrechts, A., Jayapala, M., Catthoor, F., Verkest, D.: Distributed loop controller for multi-threading in Uni-threaded ILP architectures. IEEE Trans. Comput. 58(3), 311–321 (2009)

    Article  MathSciNet  Google Scholar 

  155. Ramacher, U.: Software-defined radio prospects for multistandard mobile phones. Computer 40(10), 62–69 (2007)

    Article  Google Scholar 

  156. Ramacher, U., Raab, W., Hachmann, U., Langen, D., Berthold, J., Kramer, R., Schackow, A., Grassmann, C., Sauermann, M., Szreder, P., Capar, F., Obradovic, G., Xu, W., Bruls, N., Lee, K., Weber, E., Kuhn, R., Harrington, J.: Architecture and implementation of a software-defined radio baseband processor. In: IEEE International Symposium on Circuits and System (ISCAS), pp. 2193–2196. Infineon (2011). doi:10.1109/ISCAS.2011.5938035

  157. Ren, B., Wang, A., Bakshi, J., Liu, K., Dai, W.: A domain-specific cell based ASIC design methodology for digital signal processing applications. In: Design, Automation and Test in Europe (DATE), pp. 280–285. IEEE Computer Society (2004). doi:10.1109/DATE.2004.1269251

  158. Rigo, S., Araujo, G., Bartholomeu, M., Azevedo, R.: ArchC: a systemC-based architecture description language. In: Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), pp. 66–73 (2004). doi:10.1109/SBAC-PAD.2004.8

  159. Rixner, S., Dally, W., Khailany, B., Mattson, P., Kapasi, U., Owens, J.: Register organization for media processing. In: International Symposium on High-Performance Computer Architecture (HPCA), pp. 375–386 (2000). doi:10.1109/HPCA.2000.824366

  160. Rotenberg, E., Bennett, S., Smith, J.: Trace cache: a low latency approach to high bandwidth instruction fetching. In: IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 24–34 (1996). doi:10.1109/MICRO.1996.566447

  161. Sarkar, S., Shashank, D., Mitra, R.S., Tiwari, P.K.: Lessons and experiences with high-level synthesis. IEEE Des. Test Comput. 26(4), 34–45 (2009)

    Article  Google Scholar 

  162. Sawahashi, M., Kishiyama, Y., Taoka, H., Tanno, M., Nakamura, T.: Broadband radio access: LTE and LTE-advanced. In: International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. 224–227 (2009). doi:10.1109/ISPACS.2009.5383862

  163. Senthilvelan, M., Sima, M., Iancu, D., Hormigo, J., Schulte, M.: CORDIC instruction set extensions for matrix decompositions on Software Defined Radio processors. In: Asilomar Conference on Signals, Systems and Computers (ACSSC), pp. 1792–1797. IEEE (2009). doi:10.1109/ACSSC.2009.5470207

  164. Shabany, M., Gulak, P.G.: A 675 Mbps, 4x4 64-QAM K-Best MIMO detector in 13m CMOS. IEEE Trans. Very Large Scale Integr. Syst. 20(1), 135–147 (2010). doi:10.1109/TVLSI.2010.2090367

  165. Shanbhag, N.R.: Algorithms transformation techniques for low-power wireless VLSI systems design. Int. J. Wirel. Inf. Netw. 5, 147–171 (1998)

    Article  Google Scholar 

  166. Sheikh, F., Mill, M., Richards, B., Markovic, D., Nikolic, B.: A 1–190 MSample/s 8–64 tap energy-efficient reconfigurable FIR filter for multi-mode wireless communication. In: Symposium on VLSI Circuits, pp. 207–208 (2010). doi:10.1109/VLSIC.2010.5560297

  167. Shiun Lin, J., Hao Fang, S., Hsuan Jen, Y., Der Shieh, M.: Design of high-throughput MIMO detectors using sort-free and early-pruned techniques. In: IEEE TENCON Conference, pp. 1513–1516 (2010). doi:10.1109/TENCON.2010.5686145

  168. Silicon Hive: HiveFlex CSP Family (2010). http://www.siliconhive.com/

  169. Silicon Hive: HiveLogic Configurable Parallel Processing Platform (2010). http://www.siliconhive.com/

  170. Stotas, S., Nallanathan, A.: On the throughput and spectrum sensing enhancement of opportunistic spectrum access cognitive radio networks. IEEE Trans. Wirel. Commun. 11(1), 97–107 (2012). doi:10.1109/TWC.2011.111611.101716

    Google Scholar 

  171. Strojwas, A.J.: Cost effective scaling to 22nm and below technology nodes. In: International Symposium on VLSI Technology, Systems and Applications (VTSA), pp. 1–2. IEEE (2011). doi:10.1109/VTSA.2011.5872265

  172. Studer, C., Fateh, S., Seethaler, D.: A 757Mb/s 1.5 mm2 90 nm CMOS soft-input soft-output MIMO detector for IEEE 802.11n. In: ESSCIRC, pp. 530–533 (2010). doi:10.1109/ESSCIRC.2010.5619760

  173. Sun, Y., Cavallaro, J.R.: High-throughput soft-output MIMO detector based on path-preserving trellis-search algorithm. IEEE Trans. Very Large Scale Integr. Syst. 20(7), 1235–1247 (2012). doi:10.1109/TVLSI.2011.2147811

    Google Scholar 

  174. Suzuki, T., Yamada, H., Yamagishi, T., Takeda, D., Horisaki, K., Vander Aa, T., Fujisawa, T., Van der Perre, L., Unekawa, Y.: High throughput and low power software defined radio using dynamically reconfigurable baseband processor. IEEE Micro 31(6), 19–28 (2011). doi:10.1109/MM.2011.95

  175. Synfora/Synopsys, PICO. http://www.synopsys.com/

  176. Synopsys, Custom Designer. http://www.synopsys.com/

  177. Synopsys, Design Compiler. http://www.synopsys.com/

  178. Synopsys, IC Compiler. http://www.synopsys.com/

  179. Synopsys, IC Validator. http://www.synopsys.com/

  180. Synopsys, PrimeTime. http://www.synopsys.com/

  181. Synopsys, Symphony C Compiler. http://www.synopsys.com/Systems/

  182. Synopsys Inc.: Processor Designer Datasheet (2010). http://www.synopsys.com/

  183. Tae-Hwan, K., In-Cheol, P.: A 2.6Gb/s 1.56mm2 near-optimal MIMO detector in \(0.18{\upmu }\)m CMOS. In: IEEE Custom Integration Circuits Conference (CICC), pp. 1–4 (2010). doi:10.1109/CICC.2010.5617463

  184. Takeuchi, Y., Sakanushi, K., Imai, M.: Generation of application-domain specific instruction-set processors. In: International SoC Design Conference (ISOCC), pp. 75–78 (2010). doi:10.1109/SOCDC.2010.5682970

  185. Tao Ye, T., De Micheli, G.: Data path placement with regularity. In: IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 264–270 (2000). doi:10.1109/ICCAD.2000.896484

  186. Target ASIP development toolsuite (inc. IP Designer, IP Programmer), Target Compiler Technologies. http://www.retarget.com/

  187. Tecpanecatl-Xihuitl, J., Aguilar-Ponce, R.M., Ismail, Y., Bayoumi, M.A.: Efficient mutliplierless polyphase FIR Filter based on new distributed arithmetic architecture. In: Asilomar Conference on Signals, Systems and Computers (ACSSC), pp. 958–962. IEEE (2007). doi:10.1109/ACSSC.2007.4487361

  188. Texas Instruments: TMS320C6416 Datasheet, Rev. M (2009). http://www.ti.com/

  189. Tsai, P.Y., Chen, W.T., Lin, X.C., Huang, M.Y.: A 4x4 64-QAM reduced-complexity K-best MIMO detector up to 1.5Gbps. In: IEEE International Symposium on Circuits and System (ISCAS), pp. 3953–3956 (2010). doi:10.1109/ISCAS.2010.5537675

  190. Tsujihashi, Y., Matsumoto, H., Kato, S., Nakao, H., Kitada, O., Okazaki, K., Shinohara, H.: A high density data path generator with stretchable cells. In: IEEE Custom Integrated Circuits Conferefnce (CICC), pp. 11.3.1–11.3.4 (1992). doi:10.1109/CICC.1992.591283

  191. Tyson, G., Smelyanskiy, M., Davidson, E.: Evaluating the use of register queues in software pipelined loops. IEEE Trans. Comput. 50(8), 769–783 (2001). doi:10.1109/TC.2001.947006

    Google Scholar 

  192. Vander Aa, T.: Instruction transfer and storage exploration for low energy embeded VLIWs. Ph.D. thesis, KU Leuven (2005)

    Google Scholar 

  193. Veidenbaum, A., Nicolau, A.: Reducing power with an L0 instruction cache using history-based prediction. In: International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA), pp. 11–18 (2002). doi:10.1109/IWIA.2002.1035013

  194. van de Waerdt, J., Vassiliadis, S., Das, S., Mirolo, S., Yen, C., Zhong, B., Basto, C., van Itegem, J., Amirtharaj, D., Kalra, K., Rodriguez, P., van Antwerpen, H.: The TM3270 media-processor. In: IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 331–342 (2005). doi:10.1109/MICRO.2005.35

  195. Wang, J., Sohl, J., Kraigher, O., Liu, D.: ePUMA: A novel embedded parallel DSP platform for predictable computing. In: International Conference on Education Technology and Computer (ICETC), pp. V5-32–V5-35 (2010). doi:10.1109/ICETC.2010.5529952

  196. Wani, M., Miljanic, Z., Spasojevic, P., Redington, J.: ASIP data plane processor for multi-standard Interleaving and De-Interleaving. In: Asilomar Conference on Signals, Systems and Computers (ACSSC), pp. 1259–1263 (2010). doi:10.1109/ACSSC.2010.5757733

  197. Wei, Z., Qiang, Z., Yici, C., Xianlong, H.: A datapath routing algorithm using bit regularity extraction. In: International Conference on ASIC (ASICON), vol. 2, pp. 820–823 (2005). doi:10.1109/ICASIC.2005.1611453

  198. Weiss, O., Gansen, M., Noll, T.: A flexible datapath generator for physical oriented design. In: European Solid-State Circuits Conference (ESSCIRC), pp. 393–396 (2001)

    Google Scholar 

  199. Witte, E.M., Borlenghi, F., Ascheid, G., Leupers, R., Meyr, H.: A scalable VLSI architecture for soft-input soft-output single tree-search sphere decoding. IEEE Trans. Circuits Syst. 57(9), 706–710 (2010). doi:10.1109/TCSII.2010.2056014

    Google Scholar 

  200. Woh, M., Mahlke, S., Mudge, T., Chakrabarti, C.: Mobile supercomputers for the next-generation cell phone. Computer 43(1), 81–85 (2010). doi:10.1109/MC.2010.16

    Google Scholar 

  201. Woh, M., Sangwon, S., Mahlke, S., Mudge, T., Chakrabarti, C., Flautner, K.: AnySP: anytime anywhere anyway signal processing. IEEE Micro 30(1), 81–91 (2010)

    Article  Google Scholar 

  202. Woh, M., Yuan, L., Sangwon, S., Mahlke, S., Mudge, T., Chakrabarti, C., Bruce, R., Kershaw, D., Reid, A., Wilder, M., Flautner, K.: From SODA to Scotch: The evolution of a wireless baseband processor. In: IEEE/ACM International Symposium on Microarchitecture (MICRO), vol. 41, pp. 152–163. Department of Electrical Engineering, Arizona State University, Tempe, AZ and ARM, Ltd., Cambridge, United Kingdom (2008)

    Google Scholar 

  203. Wolff, F., Knieser, M., Weyer, D., Papachristou, C.: Codesign paradigm in digital/analog tradeoffs. In: IEEE International ASIC/SOC Conference, pp. 76–80 (1999). doi:10.1109/ASIC.1999.806478

  204. Wu, D., Eilert, J., Asghar, R., Liu, D.: VLSI implementation of a fixed-complexity soft-output MIMO detector for high-speed wireless. J. Wirel. Commun. Netw. 2010, 1–14 (2010). doi:10.1155/2010/893184

  205. Ye, T., Chaudhuri, S., Huang, F., Savoj, H., De Micheli, G.: Physical synthesis for ASIC datapath circuits. In: IEEE International Symposium on Circuits and Systems (ISCAS), vol. 3, pp. 365–368 (III) (2002). doi:10.1109/ISCAS.2002.1010236

  206. Yian Mei, L., Rosdi, B.A.B., Cheen Kok, L.: A methodology for automation structured datapath placement In VLSI design. In: IEEE Symposium on Industrial Electronics and Applications (ISIEA), pp. 273–278 (2011). doi:10.1109/ISIEA.2011.6108714

  207. Yifan, H., Yu, P., Zhenyu, Y., Londono, S., Kleihorst, R., Abbo, A., Corporaal, H.: Xetal-Pro: An ultra-low energy and high throughput SIMD processor. In: ACM/IEEE Design Automation Conference (DAC), pp. 543–548. Eindhoven University (2010)

    Google Scholar 

  208. Yoshizawa, S., Ikeuchi, H., Miyanaga, Y.: Scalable pipeline architecture of MMSE MIMO detector for 4x4 MIMO-OFDM receiver. In: IEEE International Symposium on Circuits and System. (ISCAS), pp. 2534–2537 (2010). doi:10.1109/ISCAS.2010.5537108

  209. Youness, H., Hassan, M., Sakanushi, K., Takeuchi, Y., Imai, M., Salem, A., Wahdan, A.M., Moness, M.: A high performance algorithm for scheduling and hardware-software partitioning on MPSoCs. In: International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), pp. 71–76 (2009). doi:10.1109/DTIS.2009.4938027

  210. Yu-Wen, T., Kun-Chen, W., Hui-Hsiang, T., Rung-Bin, L.: Using structured ASIC to improve design productivity. In: International Symposium on Integrated Circuits (ISIC), pp. 25–28 (2009)

    Google Scholar 

  211. Zalamea, J., Llosa, J., Ayguadé, E., Valero, M.: Two-level hierarchical register file organization for VLIW processors. In: ACM/IEEE International Symposium on Microarchitecture (MICRO), pp. 137–146 (2000). doi:10.1145/360128.360143

  212. Zhang, B., Liu, H., Zhao, H., Mo, F., Chen, T.: Domain specific architecture for next generation wireless communication. In: Design, Automation and Test in Europe (DATE), pp. 1414–1419. Group from China (2010)

    Google Scholar 

  213. Zheng, S., Zhang, Y., He, T.: The application of genetic algorithm in embedded system hardware-software partitioning. In: International Conference on Electronic Computer Technology (ICECT), pp. 219–222 (2009). doi:10.1109/ICECT.2009.132

  214. Zivojnovic, V., Pees, S., Meyr, H.: LISA-machine description language and generic machine model for HW/SW co-design. In: VLSI Signal Processing (VLSISP), pp. 127–136 (1996). doi:10.1109/VLSISP.1996.558311

  215. Zuluaga, M., Topham, N.: Design-space exploration of resource-sharing solutions for custom instruction set extensions. Trans. Comput. Aided Des. 28(12), 1788–1801 (2009). doi:10.1109/TCAD.2009.2026355

    Google Scholar 

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Fasthuber, R., Catthoor, F., Raghavan, P., Naessens, F. (2013). Background and Related Work. In: Energy-Efficient Communication Processors. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4992-8_2

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