A Planar SJ IGBT with Plugged p+ Collector
In order to improve the performance of the superjunction (SJ) Insulated Gate Bipolar Transistor (IGBT), the plugged p+ collector is implemented. By replacing the p+ collector with an optimized combination of p− and p+ collectors, it offers better blocking voltage and switching speed simultaneously. Simulation results show that the blocking voltage increases from 204 to 329 V by 61.27 % and the switching-off time reduces from 0.335 to 0.170 μs by 49.3 %. The proposed structure shows lower loss, higher breakdown voltage, and higher switching speed compared with conventional SJ IGBT. The optimized switching-off loss (E off) and V cesat trade-off makes the proposed structure suitable for high-speed and high-power applications.
This work is supported by the Guangdong Science & Technology project (2010B090400443), the Shenzhen Science & Technology Foundation (JC201005270276A) (ZD201006110039A), and the Longgang Science & technology developing Foundation.
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