Advertisement

\(2\times 6\) Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Scheme in 130 nm CMOS Process

Chapter
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

In this chapter, a continuous-time multiple-input and multiple-output crosstalk cancellation and reutilization (MIMO-XTCR) architecture operating at 2–6 Gb/s has been presented. The performance of the XTCR equalizer has been measured with various spacings of FR4 channels and data rates. The crosstalk energy reutilization (XTR) technique efficiently handles crosstalk and achieves high signal integrity in severe crosstalk environments where crosstalk had completely closed the data eye. Measurement results show improvement in \(\mathrm{{jitter}}_{p{-}p}\) and vertical opening of the eye-diagram by 67 %UI and 58.2 % respectively, which is the best known improvement to date. The MIMO-XTCR portion occupies \(0.03\,\mathrm{{mm}}^{2}\) and consumes 2.8 mW/Gbps/lane, which is 2 times lower than previously proposed XTC schemes.

Keywords

Adjacent Channel Receiver Input Linear Equalizer Decision Feedback Equalizer Forward Signal 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgments

This research was supported in part by a grant from the Semiconductor Research Corporation. The authors thank Frank O’Mahony, Bryan Casper and others at Intel Circuits Research Laboratory, Mahmoud Reza Ahmadi at AMD and Brett Hardy at LSI for technical help with this project. The authors also thank the anonymous reviewers for their constructive comments and feedback.

References

  1. 1.
    M.R. Ahmadi, A. Amirkhany, R. Harjani, A 5 Gbps 0.13 \(\upmu \)m CMOS pilot-based clock and data recovery scheme for high-speed links. IEEE J. Solid-State Circuits 45, 1533–1541 (2010)Google Scholar
  2. 2.
    J.-S. Choi, D.-K. Jeong, M.-S. Hwang, A 0.18-\(\upmu \)m CMOS 3.5-Gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method. IEEE J. Solid-State Circuits 39, 419–425 (2004)Google Scholar
  3. 3.
    K. Fukuda, T. Saito, A 12.3 mW 12.5 Gb/s complete transceiver in 65 nm CMOS, IEEE ISSCC, pp. 368–369, Feb. 2010Google Scholar
  4. 4.
    J.F. Buckwalter, A. Hajimiri, Cancellation of crosstalk-induced jitter. IEEE J. Solid-State Circuits 41, 621–631 (2006)Google Scholar
  5. 5.
    K.-I. Oh, L.-S. Kim, K.-I. Park, Y.-H. Jun, K. Kim, A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme, IEEE CICC, pp. 639–642, Sep. 2008Google Scholar
  6. 6.
    K.-J. Sham, M.R. Ahmadi, S.B.G. Talbot, R. Harjani, FEXT crosstalk cancellation for high-speed serial link design, IEEE CICC, pp. 405–408, Sep. 2006Google Scholar
  7. 7.
    C. Pfeil, BGA breakout challenges. PCB Fabrication Magazine, pp. 10–13, Oct. 2007Google Scholar

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  1. 1.Department of Electronic Engineering Kwangwoon UniversitySeoulSouth Korea
  2. 2.Department of Electronic EngineeringUniversity of MinnesotaMinneapolisUSA

Personalised recommendations