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Compilation and Synthesis for Embedded Reconfigurable Systems pp 181–195Cite as

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Abstract

This chapter presents the most relevant related work with respect to the compilation and synthesis approach developed in the context of the REFLECT project. We survey current techniques and methodologies for the mapping of computations described in high-level programming languages to reconfigurable architectures. We give particular emphasis to compilation systems that map imperative (C-like) languages to target FPGA-based systems. We also describe previous work on compiler optimizations, automated high-level synthesis, and strategies for back-end synthesis, mapping as well as placement and routing. Finally, we include an overview of EU-funded projects relevant to REFLECT.

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Authors and Affiliations

  1. Faculdade de Engenharia da Universidade do Porto, FEUP, Porto, Portugal

    João M. P. Cardoso

  2. Imperial College London, IMP, London, UK

    José Gabriel de F. Coutinho

  3. Instituto de Engenharia de Sistemas e Computadores, Investigação e Desenvolvimento em Lisboa, INESC-ID, Lisboa, Portugal

    Pedro C. Diniz

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  1. João M. P. Cardoso
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  2. José Gabriel de F. Coutinho
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  3. Pedro C. Diniz
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Correspondence to João M. P. Cardoso .

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Editors and Affiliations

  1. Faculdade de Engenharia da Universidade, R. Dr. Norberto Frias s/n,Oporto, Portuga, Porto, 4200-465, Portugal

    João Manuel Paiva Cardoso

  2. USC Information Sciences Institute, INESC-ID, Lisboa, 90292, Portugal

    Pedro C. Diniz

  3. , Department of Computing, Imperial College London, 180 Queen’s Gate, London, SW7 2RH, United Kingdom

    José Gabriel de Figueiredo Coutinho

  4. Honeywell EOOD, 64 Hristofor Columb Blvd., Sofia, 1528, Bulgaria

    Zlatko Marinov Petrov

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Cardoso, J.M.P., F. Coutinho, J.G.d., Diniz, P.C. (2013). Related Work. In: Cardoso, J., Diniz, P., de Figueiredo Coutinho, J., Petrov, Z. (eds) Compilation and Synthesis for Embedded Reconfigurable Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4894-5_7

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