This chapter describes the CoSy-based [1, 2] compilers developed in the context of the REFLECT project to support its aspect-oriented design-flow. In particular, these CoSy-based compilers are guided by LARA strategies and are responsible for generating code targeting traditional processors, as well as generating behavioral-RTL VHDL code  targeting hardware accelerators. Throughout this chapter, these compilers are referred collectively as reflectc, except when a specific compilation flow (with its specific name) is used. We also describe the compiler development extensions to support the REFLECT approach  and the weaving process controlled by LARA strategies [5–7] as described in Chap. 3.
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