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CMOS ADCs for Optical Communications

  • Yuriy M. GreshishchevEmail author
Chapter

Abstract

This paper provides a systematic view of ADCs embedded in DSP receivers of coherent optical communications systems. The functionality, performance and CMOS implementation trade-offs are discussed with the focus on techniques achieving high sampling rate and bandwidth. High conversion rate is efficiently addressed by massive interleaving of lower speed SAR ADCs, while the bandwidth limitation is dealt with on both architectural and circuit design levels. In conclusion, results of a 40 Gs/s 6b-ADC implemented in 65 nm CMOS are demonstrated.

Keywords

Source Follower Input Signal Bandwidth Hold Mode Sampling Jitter Deterministic Jitter 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgement

The author is grateful to colleagues P. Schvan, J. Aguirre, M. Besson, R. Gibbins, C. Falt, P. Flemke, N. Ben-Hamida, D. Pollex, S.-C. Wang, and J. Wolczanski for contribution to the ADC design and characterization. Special thanks to K. Roberts, B. Beggs, and J. Sitch for system insight and support.

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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.Ciena CorporationOttawaCanada

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