Abstract
CMOS technologies have been able to fabricate ultra-high-speed time-interleaved (TI) ADCs that achieve a sampling rate over 10 GS/s. The TI architecture relaxes the speed requirement for each A/D channel. It also introduces inter-channel mismatches that cause conversion errors. These errors can be reduced by calibration. An 8-channel 6-bit 16-GS/s TI ADC is presented to illustrate several circuit design and calibration techniques. Each A/D channel is a 6-bit flash ADC. The low-power comparators in the flash ADC are latches with offset calibration. A delay-locked loop generates the 8-phase sampling clocks for the TI ADC. Timing-skew calibration is used to ensure uniform sampling intervals. Both the offset calibration and the timing-skew calibration run continuously in the background. This TI ADC was fabricated using a 65 nm CMOS technology. At 16 GS/s sampling rate, this chip consumes 435 mW from a 1.5V supply. It achieves a signal-to-distortion-plus-noise ratio (SNDR) of 30.8 dB. The ADC active area is \( 0.93 \times 1.58{\text{ m}}{{\text{m}}^2} \)
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Acknowledgements
The authors thank Taiwan Semiconductor Manufacturing Company (TSMC), Hsin-Chu, Taiwan, for chip fabrication. This research was supported by the National Science Council of Taiwan, R.O.C., and by the MediaTek Research Center at National Chiao-Tung University.
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Wu, JT., Huang, CC., Wang, CY. (2013). CMOS Ultra-High-Speed Time-Interleaved ADCs. In: van Roermund, A., Baschirotto, A., Steyaert, M. (eds) Nyquist AD Converters, Sensor Interfaces, and Robustness. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4587-6_5
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DOI: https://doi.org/10.1007/978-1-4614-4587-6_5
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