CMOS Ultra-High-Speed Time-Interleaved ADCs

  • Jieh-Tsorng WuEmail author
  • Chun-Cheng Huang
  • Chung-Yi Wang


CMOS technologies have been able to fabricate ultra-high-speed time-interleaved (TI) ADCs that achieve a sampling rate over 10 GS/s. The TI architecture relaxes the speed requirement for each A/D channel. It also introduces inter-channel mismatches that cause conversion errors. These errors can be reduced by calibration. An 8-channel 6-bit 16-GS/s TI ADC is presented to illustrate several circuit design and calibration techniques. Each A/D channel is a 6-bit flash ADC. The low-power comparators in the flash ADC are latches with offset calibration. A delay-locked loop generates the 8-phase sampling clocks for the TI ADC. Timing-skew calibration is used to ensure uniform sampling intervals. Both the offset calibration and the timing-skew calibration run continuously in the background. This TI ADC was fabricated using a 65 nm CMOS technology. At 16 GS/s sampling rate, this chip consumes 435 mW from a 1.5V supply. It achieves a signal-to-distortion-plus-noise ratio (SNDR) of 30.8 dB. The ADC active area is \( 0.93 \times 1.58{\text{ m}}{{\text{m}}^2} \)


Charge Pump Conversion Gain Calibration Signal Sampling Clock Conversion Error 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



The authors thank Taiwan Semiconductor Manufacturing Company (TSMC), Hsin-Chu, Taiwan, for chip fabrication. This research was supported by the National Science Council of Taiwan, R.O.C., and by the MediaTek Research Center at National Chiao-Tung University.


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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Jieh-Tsorng Wu
    • 1
    Email author
  • Chun-Cheng Huang
    • 1
  • Chung-Yi Wang
    • 1
  1. 1.Department of Electronics EngineeringNational Chiao-Tung UniversityHsin-ChuTaiwan

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