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GS/s AD Conversion for Broadband Multi-stream Reception

  • Erwin JanssenEmail author
  • Athon Zanikopoulos
  • Kostas Doris
  • Claudio Nani
  • Gerard van der Weide
Chapter

Abstract

In this paper we present a fully integrated solution for broadband multi-stream reception, based on the direct sampling receiver architecture. The key enabler of such a solution is a 64-times interleaved 2.6 GS/s 10 b Successive-Approximation-Register ADC. The ADC combines interleaving hierarchy with an open-loop buffer array operated in feedforward-sampling and feedback-SAR mode. It is used in a fully integrated direct sampling receiver for DOCSIS 3.0 including a digital multi-channel selection filter and a PLL. The ADC achieves an SNDR of 48.5 dB and a THD of less than − 58 dB at Nyquist with an input signal of 1.4Vpp − diff. It consumes 480 mW from 1.2/1.3/1.6 V supplies and occupies an area of 5.1 mm2 in 65 nm CMOS.

Keywords

Total Harmonic Distortion Channel Selection Clock Jitter Sampling Capacitor Loop Buffer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Erwin Janssen
    • 1
    Email author
  • Athon Zanikopoulos
    • 1
  • Kostas Doris
    • 1
  • Claudio Nani
    • 2
  • Gerard van der Weide
    • 1
  1. 1.NXP SemiconductorsEindhoven, NLThe Netherlands
  2. 2.MarvellPaviaItaly

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