Impact of Statistical Variability on FinFET Technology: From Device, Statistical Compact Modelling to Statistical Circuit Simulation
New variability resilient device architectures will be required at the 22 nm CMOS technology node and beyond due to the ever-increasing statistical variability in traditional bulk MOSFETs. A TCAD-based Preliminary Design Kit (PDK) development strategy is present here for a 10 nm SOI FinFET technology, with reliable device statistical variability coming from the comprehensive 3D statistical device simulation and accurate statistical compact modelling. Results from the statistical simulation of a 6T SRAM cell demonstrate the advantages of FinFET technology.
This work was supported in part by the European Union through the EP7 Integrated Project Trams.
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