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Impact of Statistical Variability on FinFET Technology: From Device, Statistical Compact Modelling to Statistical Circuit Simulation

  • A. AsenovEmail author
  • B. Cheng
  • A. R. Brown
  • X. Wang
Chapter

Abstract

New variability resilient device architectures will be required at the 22 nm CMOS technology node and beyond due to the ever-increasing statistical variability in traditional bulk MOSFETs. A TCAD-based Preliminary Design Kit (PDK) development strategy is present here for a 10 nm SOI FinFET technology, with reliable device statistical variability coming from the comprehensive 3D statistical device simulation and accurate statistical compact modelling. Results from the statistical simulation of a 6T SRAM cell demonstrate the advantages of FinFET technology.

Notes

Acknowledgement

This work was supported in part by the European Union through the EP7 Integrated Project Trams.

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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.Department of Electronics and Electrical Engineering, Device Modelling Group, School of EngineeringUniversity of GlasgowGlasgowUK
  2. 2.Gold Standard Simulations LtdGlasgowUK

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