High Performance Piplined A/D Converters in CMOS and BiCMOS Processes
This paper describes the design approach and trade-offs in designing high-speed and high performance pipelined A/D converters in CMOS and BiCMOS processes. Design techniques to improve the linearity, lower the noise and reduce the power consumption will be discussed. The discussion will be in the context of a 16-bit 250 MS/s ADC fabricated on a 0.18 μm BiCMOS process. The ADC achieves an SNDR of 76.5 dB and consumes 850 mW from a 1.8 V supply, with an input buffer that consumes 150 mW from a 3 V supply. The measured SFDR is greater than 100 dB for input frequencies up to 100 MHz and 90 dB up to 300 MHz input frequency.
KeywordsInput Buffer Sampling Capacitance Open Loop Gain Clock Jitter Capacitor Mismatch
The author would like to acknowledge Greg Patterson, Paritosh Bhoraskar, Huseyin Dinc, Scott Puckett, Andy Morgan, Chris Dillon, Mike Hensley, Russell Stop, Scott Bardsley, David Lattimore, Jeff Bray, Carroll Speir, Robert Sneed, Val Palmer, Liam Noonan, Cindy Block, John Kornblum, Paul Wilkins, Darren Combs, Robert Shillito, and Chad Shelton at Analog Devices for their contribution to the implementation, evaluation and layout of the ADC described here.
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