High Performance Piplined A/D Converters in CMOS and BiCMOS Processes

Chapter

Abstract

This paper describes the design approach and trade-offs in designing high-speed and high performance pipelined A/D converters in CMOS and BiCMOS processes. Design techniques to improve the linearity, lower the noise and reduce the power consumption will be discussed. The discussion will be in the context of a 16-bit 250 MS/s ADC fabricated on a 0.18 μm BiCMOS process. The ADC achieves an SNDR of 76.5 dB and consumes 850 mW from a 1.8 V supply, with an input buffer that consumes 150 mW from a 3 V supply. The measured SFDR is greater than 100 dB for input frequencies up to 100 MHz and 90 dB up to 300 MHz input frequency.

Keywords

Settling Summing MDAC 

Notes

Acknowledgment

The author would like to acknowledge Greg Patterson, Paritosh Bhoraskar, Huseyin Dinc, Scott Puckett, Andy Morgan, Chris Dillon, Mike Hensley, Russell Stop, Scott Bardsley, David Lattimore, Jeff Bray, Carroll Speir, Robert Sneed, Val Palmer, Liam Noonan, Cindy Block, John Kornblum, Paul Wilkins, Darren Combs, Robert Shillito, and Chad Shelton at Analog Devices for their contribution to the implementation, evaluation and layout of the ADC described here.

References

  1. 1.
    Ali AMA et al (2010) A 16-bit 250-MS/s IF sampling pipelined ADC with background calibration. In: International solid-state circuits conference, Digest of technical papers, pp 292–293, San Francisco, USA Feb 2010Google Scholar
  2. 2.
    Ali AMA et al (2010) A 16-bit 250-MS/s IF sampling pipelined ADC with background calibration. IEEE J Solid-St Circ 45(12):2602–2612CrossRefGoogle Scholar
  3. 3.
    Ali AMA et al (2006) A 14-bit 125 MS/s IF/RF sampling pipelined ADC with 100 dB SFDR and 50 f. jitter. IEEE J Solid-St Circ 41(8):1846–1855CrossRefGoogle Scholar
  4. 4.
    Cho TB, Gray PR (1995) A 10 b, 20 Msample/s, 35 mW pipeline A/D converter. IEEE J Solid-St Circ 30(3):166–172CrossRefGoogle Scholar
  5. 5.
    Siragusa E, Galton I (2004) A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC. IEEE J Solid-St Circ 39:2126–2138CrossRefGoogle Scholar
  6. 6.
    Panigada A, Galton I (2009) A 130 mW 100 MS/s pipelined ADC with 69 dB SNDR enabled by digital harmonic distortion correction. In: International solid-state circuits conference, Digest of technical papers, San Francisco, USA pp 162–163, Feb 2009Google Scholar
  7. 7.
    Iroaga E, Murmann B (2007) A 12-Bit 75-MS/s pipelined ADC using incomplete settling. IEEE J Solid-St Circ 42(4):748–756CrossRefGoogle Scholar
  8. 8.
    Murmann B, Boser BE (2003) A 12 b 75 MS/s pipelined ADC using open-loop residue amplification. In: International solid-state circuits conference, Digest of technical papers, vol 1, San Francisco, USA pp 328–497Google Scholar

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.Analog Devices IncGreensboroUSA

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