Baseline Switching Modules and Routers

  • Giorgos Dimitrakopoulos
  • Anastasios Psarras
  • Ioannis Seitanidis


Having described the flow of data on a point-to-point link (1-to-1 connection) and the implications of each design choice, in this chapter, we move one step forward and describe the operation of modules that allow many to one and many to many connections. The operation of such modules involves, besides flow control, additional operations such as allocation and multiplexing that require the addition of extra control state per input and per output.


Output Port Switching Module Output Buffer Virtual Channel Input Buffer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. Ascia G, Catania V, Palesi M, Patti D (2008) Implementation and analysis of a new selection strategy for adaptive routing in networks-on-chip. IEEE Transactions on Computers 57(6): 809–820MathSciNetCrossRefGoogle Scholar
  2. Balkan A, QGang, UVishkin (2009) Mesh-of-trees and alternative interconnection networks for single-chip parallelism. IEEE Transactions on VLSI Systems 17(10):1419–1432Google Scholar
  3. Duato J, Yalamanchili S, Ni LM (1997) Interconnection networks - an engineering approach. IEEEGoogle Scholar
  4. Flich J, Duato J (2008) LBDR: Logic-Based Distributed Routing for NoCs. IEEE Computer Architecture Letters 7(1):13–16CrossRefGoogle Scholar
  5. Flich J, Mejia A, Lopez P, Duato J (2007) Region-based routing: An efficient routing mechanism to tackle unreliable hardware in networks on chip. In: Intern. Symp. on Networks on Chip (NOCS)Google Scholar
  6. Galles M (1997) Spider: A high-speed network interconnect. IEEE Micro 17(1)Google Scholar
  7. Huan Y, DeHon A (2012) Fpga optimized packet-switched noc using split and merge primitives. In: Int. Conf. on Field-Programmable Technology (FPT), pp 47–52Google Scholar
  8. Karol M, Hluchyj M, Morgan S (1987) Input versus output queueing on a space-division packet switch. IEEE Trans on Communications COM-35(12):1374–1356Google Scholar
  9. Medhi D, Ramasamy K (2007) Network Routing: Algorithms, Protocols, and Architectures. Morgan Kaufmann Publishers, an imprint of ElsevierGoogle Scholar
  10. Moscibroda T, Mutlu O (2009) A case for bufferless routing in on-chip networks. In: Proceedings of the 36th International Symposium on Computer Architectur, IEEEGoogle Scholar
  11. Rahimi A, Loi I, Kakoee MR, Benini L (2011) A fully-synthesizable single-cycle interconnection network for shared-l1 processor clusters. In: DATE, pp 1–6Google Scholar
  12. Roca A, Flich J, Dimitrakopoulos G (2012) Desa: Distributed elastic switch architecture for efficient networks-on-fpgas. In: 22nd Inter. Conf. on Field Programmable Logic and Applications (FPL), pp 394–399Google Scholar
  13. Vaidya AS, Sivasubramaniam A, Das CR (1999) LAPSES: A recipe for high performance adaptive router design. In: Proceedings of the 5th International Symposium on High Performance Computer Architecture (HPCA ’99), IEEE Computer Society, Washington, DC, USA, p 236Google Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Giorgos Dimitrakopoulos
    • 1
  • Anastasios Psarras
    • 1
  • Ioannis Seitanidis
    • 1
  1. 1.Electrical and Computer EngineeringDemocritus University of ThraceXanthiGreece

Personalised recommendations