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Designing 2D and 3D Network-on-Chip Architectures pp 209–236Cite as

On Designing 3-D Platforms

Abstract

Several new topologies for on-chip interconnect networks are supported by vertical integration. These three-dimensional (3-D) topologies improve the performance of an on-chip network primarily in two ways. The length of the physical links connecting the switches of the network is shorter. Additionally, the data can be routed across the on-chip network through a smaller number of switches. 3-D NoC topologies include two different types of physical links implemented with horizontal and vertical interconnects. Among others, these links exhibit differentiations in terms both of physical, as well as electrical characteristics. Though a number of topology exploration frameworks for quantifying the potential improvements from this new design paradigm, the assumptions made from the majority of them usually leads to results with considerable variation as compared to the actual 3-D platforms. On the other hand, there are only a few CAD tools for designing 3-D chips (e.g., \(\mathrm{{R}}{3}\)Logic [1]). Throughout this chapter we introduce a framework for quantifying the potential gains of employing this new design technology onto digital designs. In contrast to relevant approaches, which are mainly based on models from academic tools, the solution discussed here is based on Cadence toolflow [2].

Keywords

  • Physical Implementation
  • Virtual Layer
  • Digital Signal Processing Application
  • Topology Exploration
  • Synopsys Design Compiler

These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

This chapter was contributed by Dionysios Diamantopoulos, Kostas Siozios, George Economakos, and Dimitrios Soudris of the School of ECE, National Technical University of Athens.

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References

  1. http://www.r3logic.com/

  2. http://www.cadence.com/us/pages/default.aspx

  3. V. Pavlidis, E. Friedman, Three-dimensional Integrated Circuit Design (Morgan Kaufmann, San Francisco, 2008)

    Google Scholar 

  4. L. Zhuoyuan Li, H. Xianlong, Z. Qiang, C. Yici, B. Jinian, H. Yang, V. Pitchumani, C. Chung-Kuan, Hierarchical 3-D floorplanning algorithm for wirelength optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 53(12), 2637–2646 (2006)

    Google Scholar 

  5. J. Cong, Z. Yan, Thermal-driven multilevel routing for 3D ICs, in Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 121–126 (2005)

    Google Scholar 

  6. G. Katti, M. Stucchi, K. De Meyer, W. Dehaene, Electrical modeling and characterization of through silicon via for three-dimensional ICs. IEEE Trans. Electr. Dev. 57(1), 256–262 (2010)

    CrossRef  Google Scholar 

  7. B. Black, D. Nelson, C. Webb, N. Samra, 3D processing technology and its impact on iA32 microprocessors, in International Conference on Computer Design: VLSI in Computers and Processors (ICCD), pp. 316–318 (2004)

    Google Scholar 

  8. Y. Deng, W. Maly, 2.5D system integration: a design driven system implementation schema, in Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 450–455 (2004)

    Google Scholar 

  9. Academic tools aiming at 3-D ICs, http://proteas.microlab.ntua.gr/ksiop/software.html

  10. Y. Yonghong, G. Zhenyu, Z. Changyun, R. Dick, S. Li, ISAC: integrated space-and-time-adaptive chip-package thermal analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1), 86–99 (2007)

    CrossRef  Google Scholar 

  11. C. Ting-Yen, S. Souri, Chi On Chui, K. Saraswat, Thermal analysis of heterogeneous 3D ICs with various integration scenarios, in International Electron Devices Meeting (IEDM), pp. 31.2.1–31.2.4 (2001)

    Google Scholar 

  12. G. Link, M. Vijaykrishnan, Thermal trends in emerging technologies, in International Symposium on Quality Electronic Design (ISQED), 8 pp. (2006)

    Google Scholar 

  13. LEON3, http://www.gaisler.com

  14. N. Selvakkumaran, G. Karypis, Multiobjective hypergraph-partitioning algorithms for cut and maximum subdomain-degree minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3), 504–517 (2006)

    CrossRef  Google Scholar 

  15. K. Siozios, D. Soudris, A Tabu-based partitioning and layer assignment algorithm for 3-D FPGAs. IEEE Embed. Syst. Lett. 3(3), 97–100 (2011)

    CrossRef  Google Scholar 

  16. S. Das, A. Chandrakasan, R. Reif, Calibration of Rent’s rule models for three-dimensional integrated circuits, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, No. 4, pp. 359–366, April 2004

    Google Scholar 

  17. T. Okamoto, J. Cong, Buffered Steiner tree construction with wire sizing for interconnect layout optimization, in International Conference on Computer-Aided Design (ICCAD), pp. 44–49 (1996)

    Google Scholar 

  18. J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits, 2nd edn. (Prentice-Hall, Prentice Hall, 2003)

    Google Scholar 

  19. A. Sheibanyrad, F. Petrot, A. Jantsch, 3D Integration for NoC-Based SoC Architectures (Springer Editions, Berlin, 2011)

    CrossRef  Google Scholar 

  20. S. Gupta, M. Hilbert, S. Hong, R. Patti, Techniques for producing 3-D ICs with high-density interconnect, in International VLSI Multi-Level Interconnection Conference (2004)

    Google Scholar 

  21. SPARC V8, http://www.sparc.org/standards/V8.pdf

  22. V. Bhaskaran, K. Konstantinides, Image and Video Compression Standards: Algorithms and Architectures, 2nd edn. (Kluwer Academic, Dordrecht, 1998)

    Google Scholar 

  23. V. Ngo, H. Nguyen, H. Choi, The optimum network on chip architectures for video object plane decoder design, in International Conference on Parallel and Distributed Processing and Applications (ISPA), pp. 75–85 (2006)

    Google Scholar 

  24. S. Murali, G. De Micheli, Bandwidth-constrained mapping of cores onto NoC architectures, in Proceedings of Design, Automation and Test in Europe Conference and Exhibition, pp. 896–901 (2004)

    Google Scholar 

  25. D. Bertozzi, A. Jalabert, S. Murali, R. Tamhankar, S. Stergiou, L. Benini, G. De Micheli, NoC synthesis flow for customized domain specific multiprocessor systems-on-chip. IEEE Trans. Parallel Distrib. Syst. 16(2), 113–129 (2005)

    CrossRef  Google Scholar 

  26. I. Richardson, H.264 and MPEG-4 Video Compression: Video Coding for Next Generation Multimedia, 1st edn. (Wiley, New York, 2003)

    Google Scholar 

  27. J. Hu, R. Marculescu, Energy-and performance-aware mapping for regular NoC architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4), 551–562 (2005)

    CrossRef  Google Scholar 

  28. A. Bartzas, K. Siozios, D. Soudris, Three dimensional network-on-chip architectures, in Networks-on-Chips: Theory and Practice, ed. by F. Gebali, H. Elmiligi, M.W. El-Kharashi (CRC Press, Boca Raton, 2008)

    Google Scholar 

  29. I. Anagnostopoulos, A. Bartzas, D. Soudris, Application-specific temperature reduction systematic methodology for 2D and 3D networks-on-chip, in International Conference on Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 86–95 (2009)

    Google Scholar 

  30. A. Richard, D. Milojevic, F. Robert, A. Bartzas, A. Papanikolaou, K. Siozios, D. Soudris, Fast design space exploration environment applied on NoCs for 3D-stacked MPSoCs, Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures (2010)

    Google Scholar 

  31. R. Weerasekera, D. Pamunuwa, L. Zheng, H. Tenhynnen, Two-dimensional and three-dimensional integration of heterogeneous electronic systems under cost, performance, and technological constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(8), 1237–1250 (2009)

    Google Scholar 

  32. D. Velenis, M. Stucchi, E. Marinissen, E. Beyne, Impact of design choices on 3D SIC manufacturing cost, in Proceedings of the Workshop on 3-D Integration, at Design, Automation, and Testing in Europe (DATE), pp. 1–5 (2009)

    Google Scholar 

  33. http://3d-performance.lancs.ac.uk/

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Authors and Affiliations

  1. Department of Computer Science and Engineering, School of Applied Sciences, Frederick University, Y. Frederickou Str., Pallouriotisa 7, Nicosia, 1036, Cyprus

    Konstantinos Tatas

  2. Department of Computer Science, School of Electrical and Computer Engineering, National Technical University of Athens, Heroon Polytechneiou, Zographou Campus 9, 157 80, Athens, Greece

    Kostas Siozios & Dimitrios Soudris

  3. Department of Electronic Systems, Royal Institute of Technology, ECS/ICT/KTH Forum 120, 164 40, Kista, Sweden

    Axel Jantsch

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  1. Konstantinos Tatas
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  2. Kostas Siozios
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  3. Dimitrios Soudris
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  4. Axel Jantsch
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Correspondence to Konstantinos Tatas .

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Tatas, K., Siozios, K., Soudris, D., Jantsch, A. (2014). On Designing 3-D Platforms. In: Designing 2D and 3D Network-on-Chip Architectures. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4274-5_9

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  • DOI: https://doi.org/10.1007/978-1-4614-4274-5_9

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