NoC Verification and Testing

  • Konstantinos Tatas
  • Kostas Siozios
  • Dimitrios Soudris
  • Axel Jantsch


Verification and testing are tremendously costly steps in the design flow. In today’s multi-million gate ICs the lion’s share of design time is spent verifying the design against its specification. An inadequately verified design will lead to re-spins that could make the difference between success and failure for a product. On the other hand, manufacturing test must prevent defective parts from being shipped to customers.


Fault Model Test Vector Test Access Mechanism Design Under Verification Verification Plan 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Konstantinos Tatas
    • 1
  • Kostas Siozios
    • 2
  • Dimitrios Soudris
    • 2
  • Axel Jantsch
    • 3
  1. 1.Department of Computer Science and Engineering, School of Applied SciencesFrederick UniversityNicosiaCyprus
  2. 2.Department of Computer Science, School of Electrical and Computer EngineeringNational Technical University of AthensAthensGreece
  3. 3.Department of Electronic SystemsRoyal Institute of TechnologyKistaSweden

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