Abstract
SYSMANTIC is a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore NRE cost. Simulation and FPGA implementation results are given for four case studies of multimedia applications, proving the validity of the SYSMANTIC approach.
This chapter was contributed by Konstantinos Tatas and Costas Kyriacou from the Department of Computer Science and Engineering of Frederick University, Cyprus, and Kostas Siozios, Alexandros Bartzas and Dimitrios Soudris of the School of ECE, National Technical University of Athens.
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Tatas, K., Siozios, K., Soudris, D., Jantsch, A. (2014). The SYSMANTIC NoC Design and Prototyping Framework. In: Designing 2D and 3D Network-on-Chip Architectures. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4274-5_10
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DOI: https://doi.org/10.1007/978-1-4614-4274-5_10
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