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Power-Efficient Fault-Tolerant Finite Field Multiplier

  • Jimson Mathew
  • A. M. Jabir
  • R. A. Shafik
  • D. K. Pradhan
Chapter

Abstract

As integrated circuit density increases, digital circuits characterized by high operating frequencies and low voltage levels will be increasingly susceptible to faults. Furthermore, it has recently been shown that for many digital signature and identification schemes an attacker can inject faults into the hardware and the resulting incorrect outputs may completely expose their secrets. On-chip error masking techniques such as error correction could be one of the options to mitigate the above problems. To this end, this chapter presents a framework of techniques to design error correcting circuits. Fault attacks are based on injecting some faults into a cryptosystem and observing any leak of secret information, primarily by analyzing erroneous results produced by the cryptosystem due to the faults.

Keywords

Parity Prediction Parity Check Matrix Reed Solomon Code Triple Modular Redundancy Primitive Polynomial 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Jimson Mathew
    • 1
  • A. M. Jabir
    • 2
  • R. A. Shafik
    • 1
  • D. K. Pradhan
    • 1
  1. 1.Department of Computer ScienceUniversity of BristolBristolUK
  2. 2.Oxford Brookes UniversityOxfordUK

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