Circuit Resilience Roadmap

  • Veit B. Kleeberger
  • Christian Weis
  • Ulf Schlichtmann
  • Norbert Wehn
Chapter

Abstract

Technology scaling has an increasing impact on the resilience of integrated circuits. This growth is the result of (a) increasing sensitivity to various noise sources, and (b) an increase in parametric variability. This chapter examines the issue of circuit resilience by studying ongoing trends in technology scaling. Additional experiments with basic circuit blocks, such as memory or logic cells, reveal insights into their behavior for future technology generations and major threats for circuit resilience.

References

  1. 1.
    Asenov, A.: Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 m mosfet’s: A 3-d atomistic simulation study. IEEE Trans. Electron Devices 45(12), 2505–2513 (1998)Google Scholar
  2. 2.
    Austin, T., Blaauw, D., Mudge, T., Flautner, K.: Making typical silicon matter with Razor. IEEE Computer 37(3), 57–65 (2004)CrossRefGoogle Scholar
  3. 3.
    Dadgour, H., Endo, K., De, V., Banerjee, K.: Modeling and analysis of grain-orientation effects in emerging metal-gate devices and implications for SRAM reliability. In: IEEE International Electron Devices Meeting (IEDM), pp. 1–4 (2008)Google Scholar
  4. 4.
    Graeb, H.: Analog Design Centering and Sizing. Springer Verlag (2007)Google Scholar
  5. 5.
    Grossar, E., Stucchi, M., Maex, K., Dehaene, W.: Read stability and write-ability analysis of SRAM cells for nanometer technologies. IEEE Journal of Solid-State Circuits 41(11), 2577–2588 (2006)CrossRefGoogle Scholar
  6. 6.
    Ibe, E., Chung, S.S., Wen, S., Yamaguchi, H., Yahagi, Y., Kameyama, H., Yamamoto, S., Akioka, T.: Spreading diversity in multi-cell neutron-induced upsets with device scaling. In: IEEE Custom Integrated Circuits Conference (CICC), pp. 437–444 (2006)Google Scholar
  7. 7.
    International technology roadmap for semiconductors (2013)Google Scholar
  8. 8.
    Jan, C.-H. et al.: A 22nm SoC Platform Technology Featuring 3-D Tri-Gate and High-k/Metal Gate, Optimized for Ultra Low Power, High Performance and High Density SoC Applications. In: IEEE International Electron Devices Meeting (IEDM), pp. 44–47 (2012)Google Scholar
  9. 9.
    Kleeberger, V.B., Barke, M., Werner, C., Schmitt-Landsiedel, D., Schlichtmann, U.: Compact Model for NBTI Degradation and Recovery under Use-Profile Variations and ist Application to Aging Analysis of Digital Integrated Circuits. Microelectronics Reliability 54(6–7), pp. 1083–1089 (2014)CrossRefGoogle Scholar
  10. 10.
    Kleeberger, V.B., Graeb, H., Schlichtmann, U.: Predicting Future Product Performance: Modeling and Evaluation of Standard Cells in FinFET Technologies. In: ACM/IEEE Design Automation Conference (DAC) (2013)Google Scholar
  11. 11.
    Lu, D.D., Lin, C.H., Niknejad, A.M., Hu, C.: Compact Modeling of Variation in FinFET SRAM Cells. IEEE Design & Test of Computers 27(2), 44–50 (2010)CrossRefGoogle Scholar
  12. 12.
    Messenger, G.C.: Collection of charge on junction nodes from ion tracks. IEEE Trans. Nuclear Science, vol. 29, issue 6, pp. 2024–2031 (1982)CrossRefGoogle Scholar
  13. 13.
    Nassif, S.R., Kleeberger, V.B., Schlichtmann, U.: Goldilocks failures: Not too soft, not too hard. In: IEEE International Reliability Physics Symposium (IRPS) (2012)Google Scholar
  14. 14.
    Nassif, S.R., Mehta, N., Cao, Y.: A resilience roadmap. In: IEEE Conference on Design, Automation & Test in Europe (DATE) (2010)Google Scholar
  15. 15.
    Pehl, M.: Discrete Sizing of Analog Integrated Circuits. Ph.D. thesis, Technische Universität München (2012)Google Scholar
  16. 16.
    Predictive technology model (ptm). available at http://www.eas.asu.edu/~ptm
  17. 17.
    Saha, S.K.: Modeling process variability in scaled CMOS technology. IEEE Design & Test of Computers 27(2), 8–16 (2010)CrossRefGoogle Scholar
  18. 18.
    Sinha, S., Yeric, G., Chandra, V., Cline, B., Cao, Y.: Exploring sub-20nm FinFET design with predictive technology models. In: ACM/IEEE Design Automation Conference (DAC) (2012)Google Scholar
  19. 19.
    Wang, W., Reddy, V., Krishnan, A.T., Vattikonda, R., Krishnan, S., Cao, Y.: Compact modeling and simulation of circuit reliability for 65nm cmos technology. IEEE Trans. on Device and Materials Reliability 7(4), 509–517 (2007)CrossRefGoogle Scholar
  20. 20.
    Wann, C., Wong, R., Frank, D., Mann, R., Ko, S.B., Croce, P., Lea, D., Hoyniak, D., Lee, Y.M., Toomey, J., et al.: SRAM cell design for stability methodology. In: International Symposium on VLSI Technology (VLSI-TSA-Tech), pp. 21–22 (2005)Google Scholar
  21. 21.
    Wirth, G., Vieira, M., Neto, E., Kastensmidt, F.: Generation and propagation of single event transients in cmos circuits. In: Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE, pp. 196–201 (2006)Google Scholar
  22. 22.
    Zhang, M., Mitra, S., Mak, T., Seifert, N., Wang, N.J., Shi, Q., Kim, K.S., Shanbhag, N.R., Patel, S.J.: Sequential element design with built-in soft error resilience. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14(12), 1368–1378 (2006)CrossRefGoogle Scholar
  23. 23.
    Zhao, W., Cao, Y.: New generation of predictive technology modeling for sub-45nm early design exploration. IEEE Trans. Electron Devices 53(11), 2816–2823 (2006)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Veit B. Kleeberger
    • 1
  • Christian Weis
    • 2
  • Ulf Schlichtmann
    • 3
  • Norbert Wehn
    • 2
  1. 1.Infineon Technologies AGNeubibergGermany
  2. 2.Microelectronic Systems Design Research GroupTechnische Universität KaiserslauternKaiserslauternGermany
  3. 3.Institute for Electronic Design AutomationTechnische Universität MünchenMunichGermany

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