Circuit Resilience Roadmap

  • Veit B. KleebergerEmail author
  • Christian Weis
  • Ulf Schlichtmann
  • Norbert Wehn


Technology scaling has an increasing impact on the resilience of integrated circuits. This growth is the result of (a) increasing sensitivity to various noise sources, and (b) an increase in parametric variability. This chapter examines the issue of circuit resilience by studying ongoing trends in technology scaling. Additional experiments with basic circuit blocks, such as memory or logic cells, reveal insights into their behavior for future technology generations and major threats for circuit resilience.


Soft Error Leakage Power Static Random Access Memory Technology Node Negative Bias Temperature Instability 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



The authors want to gratefully acknowledge the contributions of Sani Nassif, Nikhil Mehta, Helmut Graeb, and Javier Varela to this work. Veit Kleeberger was employed at the Institute for Electronic Design Automation (TUM) during this work. This work was supported in part by the German Research Foundation (DFG) as part of the priority program “Dependable Embedded Systems” (SPP 1500—


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Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Veit B. Kleeberger
    • 1
    Email author
  • Christian Weis
    • 2
  • Ulf Schlichtmann
    • 3
  • Norbert Wehn
    • 2
  1. 1.Infineon Technologies AGNeubibergGermany
  2. 2.Microelectronic Systems Design Research GroupTechnische Universität KaiserslauternKaiserslauternGermany
  3. 3.Institute for Electronic Design AutomationTechnische Universität MünchenMunichGermany

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