Variability-Aware Clock Design

Chapter

Abstract

High-performance clock network design has been a challenge for many years due to the drastically increasing effect of process variability. In addition, tight power budgets have lowered supply voltage levels which make designs more sensitive to noise. Together, variability and noise present a colossal challenge to clock designers in order to meet timing, yield, and power simultaneously. This chapter discusses the different strategies that designers use to ameliorate variability and noise problems in clock network design.

Keywords

Expense Plague 

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Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  1. 1.University of California Santa CruzSanta CruzUSA
  2. 2.UFRGSPorto AlegreBrazil

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