Application of Circuit Enhancement Techniques to ADC Building Blocks
In the first section of this chapter, a 1.5-bit flash quantizer is proposed. This fully differential flash quantizer has built-in thresholds, made possible by employing inverter structures as input devices. Self-biasing techniques are employed for enhanced PVT robustness. Various analyses (confirmed with simulations) are carried out to describe the circuit’s functionality, such as, kickback noise, regeneration time, metastability, offset, sensitivity to common-mode variations, and finally, a working proof of a pipeline ADC that employs the proposed circuit in all stages is given. A design procedure is also described and the section is concluded with a performance summary and a comparative table. The second section of this chapter presents a two-stage amplifier with enhanced performance. Energy efficiency is improved by using inverter-input structures, which effectively double the transconductance of the circuit for the same current. Self-biasing is employed in both stages for improved PVT robustness and further power reduction. The analyses carried out include differential-mode and common-mode feedback, noise, offset, slew rate, input-output ranges, and some considerations are given what concerns the amplifier’s class of operation. Finally, guidelines are given for a successful design and a genetic algorithm optimization procedure is briefly described.