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Vlsi Approach for Four Quadrant Analog Multiplier for 2.4 Ghz to 2.5 Ghz

Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 150)

Abstract

Wireless communication world is revolutionized because of the design of the multiplier in the 2.4–2.5 GHz band because of the unlicensed use of the frequency band to the entire user. Multiplier is a key block of analog communication system. Multiplier mixes the signals of different frequencies or signals of different types, to strength signal for long distance communication, which emphasises the designing of more efficient and low power mixers or multipliers for RF applications. MOS RF (radio frequency) multiplier with reduces on chip area operate at ISM Band frequency with high linearity. A 2.4–2.50 GHz band (ISM BAND) multiplier designed and simulated on tanner tool 13. The simulations results presented here are for 1–10 GHz. The circuit is implemented using 180 nm level 3 models and simulated in TSPICE simulator. The transistor operating in linear region reduces the drain current and also the power consumption with large input range. Power consumption is reduces to 68.57 μW.

Keywords

Analog multiplier ISM band Quadrant RF (radio frequency) 

References

  1. 1.
    Sawigun C, Demosthenous A (2007) Compact low-voltage CMOS four-quadrant analog multiplier”, 2007 IEEE, pp 751–754Google Scholar
  2. 2.
    Ebrahimi A, Naimi HM (2010) 1.2 V single supply and low power CMOS four-quadrant analog multiplier. In: 2010 XIth international workshop on symbolic and numerical methods, modeling and applications to circuit design (SM2ACD), pp 978–983Google Scholar
  3. 3.
    Hidayat R, Dejhan K, Moungnoul1 P, Miyanaga Y (2007) A GHz analog multiplier for UWB communications. In: Proceedings of Asia-Pacific conference on communications, pp 55–58Google Scholar
  4. 4.
    Akshatha BC, Vijay Kumar A (2009) Low voltage, low power, high linearity, high speed CMOS voltage mode analog multiplier. In: Second international conference on emerging trends in engineering and technology, ICETET-09, pp 149–154Google Scholar
  5. 5.
    Lau KT, Lee ST, Ong VKS (1998) Our-quadrant analogue CMOS multiplier cell for VLSI signal and information processing. IEEE Proc Circ Device Sys 145(2):132–134CrossRefGoogle Scholar
  6. 6.
    Chen C, Li Z, (2006) A low-power CMOS analog multiplier. IEEE Trans Circ Sys Exp Briefs 53(2):100–104Google Scholar

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.VLSI, G. H. Raisoni College of EngineeringNagpurIndia
  2. 2.Department of ElectronicsG. H. Raisoni College of EngineeringNagpurIndia

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