Effect of Temperature on Si-Ge Hetero-Gate Raised Buried Oxide Drain Tunnel FET Electrical Parameters

Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 150)

Abstract

The effect of temperature on SiGe hetero-gate raised buried oxide drain Tunnel FET electrical parameters like tunnelling bandgap, threshold voltage, subthreshold swing, etc. are discussed in this paper. A modified SOI based Silicon hetero-gate TFET structure has been used. The proposed device is almost free from short channel effects. The simulation is performed using Synopsys 2D TCAD tools where non local band-to-band tunnelling is applied.

Keywords

Non local band-to-band tunnelling Hetero-gate Raised buried oxide Tunnel FET SiGe 

Notes

Acknowledgments

This work was supported by ALL INDIA COUNCIL FOR TECHNICAL EDUCATION (AICTE), under Grant 8023/BOR/RID/RPS-253/2008-09.

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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringNational Institute of TechnologySilcharIndia

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