Effect of Temperature on Si-Ge Hetero-Gate Raised Buried Oxide Drain Tunnel FET Electrical Parameters

Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 150)


The effect of temperature on SiGe hetero-gate raised buried oxide drain Tunnel FET electrical parameters like tunnelling bandgap, threshold voltage, subthreshold swing, etc. are discussed in this paper. A modified SOI based Silicon hetero-gate TFET structure has been used. The proposed device is almost free from short channel effects. The simulation is performed using Synopsys 2D TCAD tools where non local band-to-band tunnelling is applied.


Non local band-to-band tunnelling Hetero-gate Raised buried oxide Tunnel FET SiGe 



This work was supported by ALL INDIA COUNCIL FOR TECHNICAL EDUCATION (AICTE), under Grant 8023/BOR/RID/RPS-253/2008-09.


  1. 1.
    Vandamme EP, Jansen P, Deferm L (1997) Modelling the subthreshold swing in MOSFET’s. IEEE Electr Dev Lett 18:369–371Google Scholar
  2. 2.
    Gopalakrishnan K, Woo R, Jungemann C, Griffin PB(2005) JD Plummer, impact ionization MOS (I-MOS) -part II: experimental results. IEEE T Electron Dev 52:77–84CrossRefGoogle Scholar
  3. 3.
    Kam H, Lee DT, Howe RT, King T-J (2005) A new nano electromechanical-field effect transistor (NEMFET) design for low power electronics. In: IEDM Technical Digest pp 463–466Google Scholar
  4. 4.
    Abele N, Fritschi N, Boucart K, Casset F, Ancey P, Ionescu AM (2005) Suspended-gate MOSFET, bringing new MEMS functionality into solid-state MOS transistor. In: IEDM Technical Digest pp 1075–1077Google Scholar
  5. 5.
    Choi WY, Park BG, Lee JD, Liu TJK (2007) Tunneling field effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. , IEEE Electr Dev Lett 28:743–745Google Scholar
  6. 6.
    Qin Z, Wei Z, Seabaugh A (2006) Low-subthreshold-swing tunnel transistors. IEEE Electr Dev Lett 27(4):297–300Google Scholar
  7. 7.
    Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors (ITRS). available at www.itrs.net
  8. 8.
    Ashburn P (2004) SiGe heterojunction bipolar transistor. John Wiley & Sons, Ltd, ChichesterGoogle Scholar
  9. 9.
    Zhang, Q., Suta, S., Kosel, T., Seabaugh, A.: Fully-depleted Ge interband tunnel transistor modeling and junction formation. Solid State Electron, vol. 53, pp. 30-35 (2009).CrossRefGoogle Scholar
  10. 10.
    Synopsys TCAD sentaurus device manual (2010).Google Scholar
  11. 11.
    SOI Technology, Materials to VLSI, 3rd edn Jean-Pierre Colinge, Springer International, HeidelbergGoogle Scholar
  12. 12.
    Tsividis Y (1999) Operation and modelling of the MOS transistor. 2nd edn, McGraw Hill, New YorkGoogle Scholar
  13. 13.
    Bhowmick B, Baishya S (2012) A physics–based model for electrical parameters of double gate hetero-material nano scale tunnel FET. Int J Appl Inform Syst 3:28–32Google Scholar

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringNational Institute of TechnologySilcharIndia

Personalised recommendations