Abstract
By default, each path is timed for a single cycle, i.e., data launched at any edge of the clock should be captured by the next flop at the next rising edge of the clock on the destination flop. Figure 12.1 shows this relationship.
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© 2013 Springer Science+Business Media New York
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Gangadharan, S., Churiwala, S. (2013). Multi Cycle Paths. In: Constraining Designs for Synthesis and Timing Analysis. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-3269-2_12
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DOI: https://doi.org/10.1007/978-1-4614-3269-2_12
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