Disruptive Architectural Proposals and Performance Analysis

  • Pierre-Emmanuel Gaillardon
  • Ian O’Connor
  • Fabien Clermidy


In this chapter, we explore disruptive architecture proposals. In the previous chapter, we showed that it is possible to obtain very compact reconfigurable in-field computation cells. Since these cells require architectural modifications, we proposed an architecture for this compact logic, characterized by the association of a logic layer, to adapt the granularity and the use of fixed interconnection topologies to reduce the routing impact. To compare this approach with conventional FPGAs in an objective way, it was necessary to develop a specific toolflow suited to our requirements, able to describe the designed architecture. Based on the VTR toolflow, the tool integrates fixed topology routing and the specific organization of the layered architecture. Benchmarking simulations were performed. In a first approach, a local exploration of the proposed layer is done, in order to study the impact of the fixed interconnect topologies. We showed that the Modified Omega topology gives the best mapping rates on the structure with about 90% of mapping success for 6-node graphs. In a second approach, complete architectural benchmarking was conducted and we showed that the proposed architecture leads to an improvement, in area saving, of 46% in average, with respect to CMOS. We also discovered that the routing delay is less distributed and tends to be more controllable than in the traditional approach.


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Copyright information

© Springer Science+Business Media New York 2012

Authors and Affiliations

  • Pierre-Emmanuel Gaillardon
    • 1
  • Ian O’Connor
    • 2
  • Fabien Clermidy
    • 3
  1. 1.INF 339 (Bâtiment INF)EPFL IC ISIM LSI1LausanneSwitzerland
  2. 2.Bâtiment F7INL, Site Ecole Centrale de LyonEcullyFrance
  3. 3.CEA-LETIMINATECGrenobleFrance

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