Multi-Bit Quantizer Design for Continuous-Time Sigma-Delta Modulators with Reduced Device Matching Requirements

  • Marvin Onabajo
  • Jose Silva-Martinez
Chapter

Abstract

Future wireless devices will require extensive connectivity to accommodate several services, which means that the receivers must cover broader frequency bands. Therefore, on-chip analog-to-digital converters (ADCs) in multi-standard receivers not only demand increased signal-to-quantization-noise-ratio, but also more bandwidth for the conversion of the analog signals into the digital domain. This chapter briefly introduces a lowpass continuous-time ΣΔ ADC architecture that was developed for next generation broadband receiver applications. Rather than using multiple signal levels, a multi-bit digital-to-analog converter (DAC) realization based on a feedback signal with time-varying pulse duration was employed. This approach alleviates nonlinearity problems associated with typical multi-bit DACs. The chapter also contains an in-depth description of the corresponding 3-bit quantizer architecture with multi-phase clocking. The reference levels for this quantizer are adjustable to compensate for process variations after fabrication if the application necessitates fine resolution.

Keywords

Expense Summing Polysilicon 

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Copyright information

© Springer Science+Business Media New York 2012

Authors and Affiliations

  • Marvin Onabajo
    • 1
  • Jose Silva-Martinez
    • 2
  1. 1.Department of Electrical and Computer Engineering, 409 Dana Research CenterNortheastern UniversityBostonUSA
  2. 2.Department of Electrical and Computer EngineeringTexas A&M UniversityCollege StationUSA

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