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Differential 77-GHz High-Linearity Receiver Front-End

  • Dietmar Kissinger
Chapter
Part of the SpringerBriefs in Electrical and Computer Engineering book series (BRIEFSELECTRIC)

Abstract

A novel high-linearity architecture for integrated 77 GHz receiver front-ends in SiGe technology is presented. The fabricated chip can be operated in differential or single-ended mode and on-wafer measurements show a gain of 24 dB and a noise figure of 14 dB when driven single-ended with an LO power of 0 dBm. An input related 1 dB compression point of − 10 dBm is achieved with a total power consumption of 132 mW from a 3.3 V supply. The overall occupied chip area is 728 × 1028 μ m2. In comparison to other published receiver front-ends the performance related figure of merit of this work is among the highest published so far. In addition, it simultaneously achieves the best performance to power consumption ratio.

Keywords

Noise Figure Conversion Gain Cascode Stage SiGe Technology Power Consumption Ratio 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  • Dietmar Kissinger
    • 1
  1. 1.University of Erlangen-NurembergErlangenGermany

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