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High-Sigma Verification and Design

The Accuracy of Five Billion Monte Carlo Samples in Minutes
  • Trent McConaghyEmail author
  • Kristopher Breen
  • Jeffrey Dyck
  • Amit Gupta
Chapter

Abstract

High-sigma IC designs are inherently difficult to create and verify. This chapter reviews various approaches for high-sigma analysis. It then describes High-Sigma Monte Carlo (HSMC), which is a high-sigma analysis approach that is fast, accurate, scalable, and verifiable. This chapter presents example results for representative high-sigma designs, revealing some of the key traits that make the HSMC technology effective. It describes how to extract full PDFs from −6 to +6 sigma, for application to statistical system-level analysis (e.g. for memory arrays). Finally, it presents industrial design examples.

Keywords

Monte Carlo Process Point Setup Time Importance Sampling Monte Carlo Sample 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. Abu-Rahma MH, Chowdhury K, Wang J, Chen Z, Yoon SS, Anis M (2008) A methodology for statistical estimation of read access yield in SRAMs. In: Proceedings of design automation conference (DAC), June 2008, pp 205–210Google Scholar
  2. Aitken RC, Idgunji S (2007) Worst-case design and margin for embedded SRAM. In: Proceedings of design automation and test in Europe (DATE), March 2007, pp 1289–1294Google Scholar
  3. Bai X, Patel P, Zhang X (2012) A new statistical setup and hold time definition. In: Proceedings of international conference on integrated circuit design and technology (ICICDT), May 2012Google Scholar
  4. Celis M, Dennis JE, Tapia RA (1985) A trust region strategy for nonlinear equality constrained optimization. In: Boggs P, Byrd R, Schnabel R (eds) numerical optimization, SIAM, Philadelphia, pp 71–82Google Scholar
  5. Drennan PG, McAndrew CC (2003) Understanding MOSFET mismatch for analog design. IEEE J Solid State Circuits 38(3):450–456CrossRefGoogle Scholar
  6. Gu C, Roychowdhury J (2008) An efficient, fully nonlinear, variability-aware non-Monte-Carlo yield estimation procedure with applications to SRAM cells and ring oscillators. In: Proceedings of Asia-South Pacific design automation conference (ASP-DAC), pp 754–761Google Scholar
  7. Hastie T, Tibshirani R, Friedman J (2009) The elements of statistical learning, 2nd edn. Springer, NYGoogle Scholar
  8. Hesterberg TC (1988) Advances in importance sampling. PhD Dissertation, Statistics Department, Stanford UniversityGoogle Scholar
  9. Hohenbichler M, Rackwitz R (1982) First-order concepts in system reliability. Struct Saf 1(3):177–188CrossRefGoogle Scholar
  10. Hocevar DE, Lightner MR, Trick TN (1983) A study of variance reduction techniques for estimating circuit yields. IEEE Trans Comput Aided Des Integr Circ Syst 2(3):180–192CrossRefGoogle Scholar
  11. Kanj R, Joshi RV, Nassif SR (2006) Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events. In: Proceedings of design automation conference (DAC), June 2006, pp 69–72Google Scholar
  12. Kanoria Y, Mitra S, Montanari A (2010) Statistical static timing analysis using Markov Chain Monte Carlo. In: Proceedings of design automation and test in Europe (DATE), March 2010Google Scholar
  13. Li X (2010) Maximum-information storage system: concept, implementation and application. In: Proceedings of international conference on computer-aided design (ICCAD), pp 39–46Google Scholar
  14. Li X (2011) Rethinking memory redundancy: optimal bit cell repair for maximum-information storage. In: Proceedings of design automation conference (DAC), pp 316–321Google Scholar
  15. McConaghy T (2011) High-dimensional statistical modeling and analysis of custom integrated circuits. In: Proceedings of custom integrated circuits conference (CICC), September 2011, pp 1–8 (invited paper)Google Scholar
  16. Metropolis N, Rosenbluth AW, Rosenbluth MN, Teller E (1953) Equations of state calculations by fast computing machines. J Chem Phys 21(6):1087–1092CrossRefGoogle Scholar
  17. Niederreiter H (1992) Random number generation and quasi-Monte Carlo methods. Society for Industrial and Applied Mathematics (SIAM), PhiladelphiaGoogle Scholar
  18. Qazi M, Tikekar M, Dolecek L, Shah D, Chandrakasan A (2010) Loop flattening and spherical sampling: highly efficient model reduction techniques for SRAM yield analysis. In: Proceedings of design automation and test in Europe (DATE), March 2010Google Scholar
  19. Schenkel F et al (2001) Mismatch analysis and direct yield optimization by spec-wise linearization and feasibility-guided search. In: Proceedings of design automation conference (DAC), pp 858–863Google Scholar
  20. Singhee A, Rutenbar RA (2009) Statistical blockade: very fast statistical simulation and modeling of rare circuit events, and its application to memory design. IEEE Trans Comput Aided Des 28(8):1176–1189CrossRefGoogle Scholar
  21. Solido Design Automation Inc. (2012) Variation designer. http://www.solidodesign.com
  22. Synopsys Inc. (2012) Synopsys® HSPICE®. http://www.synopsys.com
  23. Wang J, Yaldiz S, Li X, Pileggi L (2009) SRAM parametric failure analysis. In: Proceedings of design automation conference (DAC), June 2009Google Scholar
  24. Wilson EB (1927) Probable inference, the law of succession, and statistical inference. J Am Statist Assoc 22:209–212CrossRefGoogle Scholar
  25. Zuber P, Dobrovolný P, Miranda M (2010) A holistic approach for statistical SRAM analysis. In: Proceedings of design automation conference (DAC), June 2010, pp 717–722Google Scholar

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Trent McConaghy
    • 1
    Email author
  • Kristopher Breen
    • 2
  • Jeffrey Dyck
    • 3
  • Amit Gupta
    • 3
  1. 1.Solido Design Automation Inc.SaskatoonCanada
  2. 2.Solido Design Automation Inc.SaskatoonCanada
  3. 3.Solido Design Automation Inc.SaskatoonCanada

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