Mitigation of Timing Skew
In this chapter, sources of timing skew are discussed, and it is shown that the resulting timing skew is detrimental for ADCs with high-speed input signals. A statistics-based background calibration algorithm which mitigates the effect of timing skew is then presented with analysis on the various aspects of the algorithm. The chapter concludes with some of the requirements on the input signal such that the algorithm functions properly.
KeywordsInput Signal Calibration Algorithm Sampling Edge Reference Clock Inverter Chain
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