Mitigation of Timing Skew

  • Manar El-Chammas
  • Boris Murmann
Part of the Analog Circuits and Signal Processing book series (ACSP)


In this chapter, sources of timing skew are discussed, and it is shown that the resulting timing skew is detrimental for ADCs with high-speed input signals. A statistics-based background calibration algorithm which mitigates the effect of timing skew is then presented with analysis on the various aspects of the algorithm. The chapter concludes with some of the requirements on the input signal such that the algorithm functions properly.


Input Signal Calibration Algorithm Sampling Edge Reference Clock Inverter Chain 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  1. 1.Texas Instruments, Inc.DallasUSA
  2. 2.Department of Electrical EngineeringStanford UniversityStanfordUSA

Personalised recommendations