Abstract
In this chapter, a model for time-interleaved ADCs is presented. Frequency domain analysis is used to illustrate how time-varying errors, such as gain, offset, and timing skew, affect the resulting time-interleaved ADC output. Expressions relating the different errors to ADC performance and bounds on the magnitude of these errors are also derived for wide-sense stationary (WSS) signals, and simulations are used to demonstrate the accuracy of these expressions. Thus, for the given set of ADC specifications required by serial links, these expressions can be used to calculate the acceptable timing skew, such that it does not limit the performance of the time-interleaved ADC.
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© 2012 Springer Science+Business Media, LLC
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El-Chammas, M., Murmann, B. (2012). Time-Interleaved ADCs. In: Background Calibration of Time-Interleaved Data Converters. Analog Circuits and Signal Processing. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1511-4_2
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DOI: https://doi.org/10.1007/978-1-4614-1511-4_2
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Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-1510-7
Online ISBN: 978-1-4614-1511-4
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