Implementation: A WiMAX/WLAN/LTE Synthesizer
The architecture presented in the previous chapter serves as a basis for the work on the schematic and the layout. In order to prove the working of the architecture within the practical means, it has been reduced to its main parts and the focus of this work is shown in Fig. 9.1. The whole design is implemented in a 0.18 μm CMOS process with 1.8 V biasing only (no 3.3 V structures are used).
As can be seen, there are some implementation-related information added. The different block fillings indicate the different power domains. Some parts of the low-pass filters are placed outside the chip as well as the ΣΔM itself thus enabling more observability and controllability. There are also several tap points for debugging.
Since this reduced architecture is based on the previous one, all the analysis and block-level design done so-far apply here also. Therefore, we now go into some of the important blocks, their schematic design and their layout.
KeywordsPhase Noise Tuning Curve Charge Pump Loop Filter Wide Tuning Range
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