Advertisement

Implementation: A WiMAX/WLAN/LTE Synthesizer

  • Jad G. Atallah
  • Mohammed Ismail
Chapter
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

The architecture presented in the previous chapter serves as a basis for the work on the schematic and the layout. In order to prove the working of the architecture within the practical means, it has been reduced to its main parts and the focus of this work is shown in Fig. 9.1. The whole design is implemented in a 0.18 μm CMOS process with 1.8 V biasing only (no 3.3 V structures are used).

As can be seen, there are some implementation-related information added. The different block fillings indicate the different power domains. Some parts of the low-pass filters are placed outside the chip as well as the ΣΔM itself thus enabling more observability and controllability. There are also several tap points for debugging.

Since this reduced architecture is based on the previous one, all the analysis and block-level design done so-far apply here also. Therefore, we now go into some of the important blocks, their schematic design and their layout.

Keywords

Phase Noise Tuning Curve Charge Pump Loop Filter Wide Tuning Range 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Sjoland H (2002) Improved switched tuning of differential CMOS VCOs. IEEE Trans Circuits Syst II: Analog Digital Signal Process 49(5):352–355CrossRefGoogle Scholar
  2. 2.
    Johns D, Martin KW (1997) Analog integrated circuit design. Wiley, New YorkGoogle Scholar
  3. 3.
    Nicolson S, Khoman P (2004) Improvements in biasing and compensation of CMOS opamps. In: Proceedings of the 2004 international symposium on circuits and systems (ISCAS ’04), Vancouver, vol 661, pp 665–668Google Scholar
  4. 4.
    Rhee W (1999) Design of high-performance CMOS charge pumps in phase-locked loops. In: Proceedings of the 1999 IEEE international symposium on circuits and systems (ISCAS ’99), Orlando, vol 542, pp 545–548Google Scholar
  5. 5.
    Perraud L, Bonnot JL, Sornin N, Pinatel C (2003) Fully integrated 10 GHz CMOS VCO for multi-band WLAN applications. In: Proceedings of the 29th European solid-state circuits conference (ESSCIRC ’03), Estoril, pp 353–356Google Scholar
  6. 6.
    Stojanovic V, Oklobdzija VG (1999) Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems. IEEE J Solid State Circuits 34(4):536–548CrossRefGoogle Scholar
  7. 7.
    Vaucher CS, Ferencic I, Locher M, Sedvallson S, Voegeli U, Wang Z (2000) A family of low-power truly modular programmable dividers in standard 0.35um CMOS technology. IEEE J Solid State Circuits 35(7):1039–1045CrossRefGoogle Scholar
  8. 8.
    Bou Sleiman S, Atallah JG, Rodriguez S, Rusu A, Ismail M (2008) Wide-division-range high-speed fully programmable frequency divider. Paper presented at the Joint IEEE NEWCAS and TAISA conference, MontrealGoogle Scholar
  9. 9.
    Navarro Soares J Jr, Van Noije WAM (1999) A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC). IEEE J Solid State Circuits 34(1):97–102CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2012

Authors and Affiliations

  • Jad G. Atallah
    • 1
  • Mohammed Ismail
    • 2
  1. 1.Notre Dame University - LouaizeZouk MosbehLebanon
  2. 2.The Ohio State UniversityColumbusUSA

Personalised recommendations