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SyReC: A Programming Language for Synthesis of Reversible Circuits

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System Specification and Design Languages

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 106))

Abstract

Reversible logic serves as a basis for emerging technologies like quantum computing and additionally has applications in low-power design. In particular, since conventional technologies like CMOS are going to reach their limits in the near future, reversible logic has been established as a promising alternative. Thus, in the last years this area started to become intensely studied by researchers. In particular, how to efficiently synthesize complex reversible circuits is an important question. So far, only synthesis approaches are available that rely on Boolean function representations, like e.g., truth tables or decision diagrams.

In this chapter, we propose the programming language SyReC that allows to specify and afterwards to automatically synthesize reversible circuits. Using an existing programming language for reversible software design as basis, we introduce new concepts, operations, and restrictions allowing the specification of reversible hardware. Furthermore, a hierarchical approach is presented that automatically transforms the respective statements and operations of the new programming language into a reversible circuit. Experiments show that with the proposed method, complex circuits can be easily specified and synthesized while with previous approaches this often is not possible due to the limits caused by truth tables or decision diagrams.

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Notes

  1. 1.

    Note that we focus thereby on the concepts of the language. A detailed technical definition of SyReC can be found at RevLib.org [32].

  2. 2.

    These extensions are not necessarily needed (i.e., they can also be expressed by the existing operations), but they allow a more intuitive programming of reversible circuits.

  3. 3.

    Figure 13.5a shows the notation for a single bit operation. For larger bit-widths the notation is extended accordingly.

  4. 4.

    A similar comparison to alternative approaches (e.g., [11,  8]) was not possible since due to memory limitations the respective benchmarks cannot be represented in terms of truth tables which is required by these approaches.

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Acknowledgment

This work was supported by the German Research Foundation (DFG) (DR 287/20-1).

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Authors and Affiliations

  1. Institute of Computer Science, University of Bremen, 28357, Bremen, Germany

    Robert Wille, Sebastian Offermann & Rolf Drechsler

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  1. Robert Wille
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  2. Sebastian Offermann
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  3. Rolf Drechsler
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Correspondence to Robert Wille .

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Editors and Affiliations

  1. University of Southampton, Southampton, United Kingdom

    Tom J. Kaźmierski

  2. ECSI, Gières, France

    Adam Morawiec

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Wille, R., Offermann, S., Drechsler, R. (2012). SyReC: A Programming Language for Synthesis of Reversible Circuits. In: Kaźmierski, T., Morawiec, A. (eds) System Specification and Design Languages. Lecture Notes in Electrical Engineering, vol 106. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1427-8_13

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  • DOI: https://doi.org/10.1007/978-1-4614-1427-8_13

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