Abstract
This chapter presents an approach for back-annotating timing information determined from optimized binary code into the source code of the software. The annotated source code can be integrated into a SystemC-based simulation environment and allows a fast execution time estimation while preserving timing accuracy. In contrast to previous approaches, the presented method supports heavily optimized code without any need for changes in the compiler. To annotate timing data, the relation between source code and binary code is reconstructed using data flow analysis. Based on debug information, the analysis allows correlating the execution of source code lines with the control flow on binary level. An experimental evaluation of this technique provided encouraging results as the produced timing estimates deviate less than 6% from the results of a cycle-accurate instruction set simulator.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
A basic block is a sequence of instructions in which the control flow enters only at the beginning and leaves at the end with no possibility of branching except at the end.
References
Open SystemC Initiative (OSCI): http://www.systemc.org.
Synopsys CoMET: http://www.synopsys.com.
Imperas Open Virtual Platforms (OVP): http://www.ovpworld.org.
Z. Wang, A. Sanchez, and A. Herkersdorf, “SciSim: A Software Performance Estimation Framework Using Source Code Instrumentation,” WOSP ’08: Proceedings of the 7th International Workshop on Software and Performance.
J. Schnerr, O. Bringmann, A. Viehl, and W. Rosenstiel, “High-Performance Timing Simulation of Embedded Software,” DAC ’08: Proceedings of the 45th annual ACM/IEEE Design Automation Conference.
T. Meyerowitz, A. Sangiovanni-Vincentelli, M. Sauermann, and D. Langen, “Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor,” DATE ’08: Proceedings of the Conference on Design, Automation and Test in Europe.
K.-L. Lin, C.-K. Lo, and R.-S. Tsay, “Source-Level Timing Annotation for Fast and Accurate TLM Computation Model Generation,” ASP-DAC ’10: Proceedings of the 15th Asia and South Pacific Design Automation Conference.
J. Castillo, H. Posadas, E. Villar, and M. Martinez, “Fast Instruction Cache Modeling for Approximate Timed HW/SW Co-Simulation,” GLSVLSI ’10: Proceedings of the 20th Great lakes symposium on VLSI.
Z. Wang, K. Lu, and A. Herkersdorf, “An Approach to Improve Accuracy of Source-Level TLMs of Embedded Software,” DATE ’11: Proceedings of the Conference on Design, Automation and Test in Europe.
E. Cheung, H. Hsieh, and F. Balarin, “Memory Subsystem Simulation in Software TLM/T Models,” ASP-DAC ’09: Proceedings of the 14th Asia and South Pacific Design Automation Conference.
A. Bouchhima, P. Gerin, and F. Petrot, “Automatic Instrumentation of Embedded Software for High Level Hardware/Software Co-Simulation,” ASP-DAC ’09: Proceedings of the 14th Asia and South Pacific Design Automation Conference.
Z. Wang and A. Herkersdorf, “An Efficient Approach for System-Level Timing Simulation of Compiler-Optimized Embedded Software,” DAC ’09: Proceedings of the 46th annual ACM/IEEE Design Automation Conference.
AbsInt aiT WCET Analyzer: http://www.absint.com/ait/.
Tidorum Bound-T: http://www.bound-t.com/.
A. Viehl, M. Pressler, and O. Bringmann, “Bottom-Up Performance Analysis Considering Time Slice Based Software Scheduling at System Level,” CODES+ISSS ’09: Proceedings of the 7th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis.
R. Henia, A. Hamann, M. Jersak, R. Racu, K. Richter, and R. Ernst, “System Level Performance Analysis - the SymTA/S Approach,” IEE Proceedings Computers and Digital Techniques, vol. 152, no. 2, pp. 148–166.
E. Wandeler, L. Thiele, M. Verhoef, and P. Lieverse, “System Architecture Evaluation Using Modular Performance Analysis: a Case Study,” International Journal on Software Tools for Technology Transfer (STTT), vol. 8, no. 6, pp. 649–667, 2006.
R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister, and C. Ferdinand, “Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 7, pp. 966 –978.
The DWARF Debugging Standard Version 3: http://dwarfstd.org/doc/Dwarf3.pdf
libdwarf: http://reality.sgiweb.org/davea/dwarf.html.
F. Martin, “Generating Program Analyzers,” Ph.D. dissertation, Saarland University, 1999.
Mälardalen Worst-Case Execution Time research group WCET Benchmark Suite: http://www.mrtc.mdh.se/projects/wcet/benchmarks.html.
GNUARM GCC-4.0 Toolchain: http://www.gnuarm.com/.
ARM RealView Development Suite: http://www.arm.com/.
DEBIE-1 DPU Software Worst-Case Execution Time Benchmark: http://www.mrtc.mdh.se/projects/WCC08/doku.php?id=bench:debie1.
Y.-T. S. Li and S. Malik, “Performance Analysis of Embedded Software using Implicit Path Enumeration,” DAC ’95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference.
S. Stattelmann, O. Bringmann, and W. Rosenstiel, “Fast and Accurate Resource Conflict Simulation for Performance Analysis of Multi-Core Systems,” DATE ’11: Proceedings of the Conference on Design, Automation and Test in Europe.
S. Stattelmann, O. Bringmann, and W. Rosenstiel, “Fast and Accurate Source-Level Simulation of Software Timing Considering Complex Code Optimizations,” DAC ’11: Proceedings of the 48th annual ACM/IEEE Design Automation Conference.
B. Sander, J. Schnerr, and O. Bringmann, “ESL Power Analysis of Embedded Processors for Temperature and Reliability Estimations,” CODES+ISSS ’09: Proceedings of the 7th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis.
Acknowledgment
This work has been partially supported by the BMBF project SANITAS under grant 01M3088C and by the ITEA/BMBF project VERDE under grant 01|S09012A.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer Science+Business Media, LLC
About this paper
Cite this paper
Stattelmann, S., Viehl, A., Bringmann, O., Rosenstiel, W. (2012). Towards Accurate Source-Level Annotation of Low-Level Properties Obtained from Optimized Binary Code. In: Kaźmierski, T., Morawiec, A. (eds) System Specification and Design Languages. Lecture Notes in Electrical Engineering, vol 106. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1427-8_11
Download citation
DOI: https://doi.org/10.1007/978-1-4614-1427-8_11
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-1426-1
Online ISBN: 978-1-4614-1427-8
eBook Packages: EngineeringEngineering (R0)