Abstract
We introduce CAPH, a new domain-specific language (DSL) suited to the implementation of stream-processing applications on field programmable gate arrays (FPGA). CAPH relies upon the actor/dataflow model of computation. Applications are described as networks of purely dataflow actors exchanging tokens through unidirectional channels. The behavior of each actor is defined as a set of transition rules using pattern matching. The CAPH suite of tools currently comprises a reference interpreter and a compiler producing both SystemC and synthetizable VHDL code. We describe the implementation, with a preliminary version of the compiler, of a simple real-time motion detection application on an FPGA-based smart camera platform. The language reference manual and a prototype compiler are available from http://wwwlasmea.univ-bpclermont.fr/Personnel/Jocelyn.Serot/caph.html.
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- 1.
CAPH is a recursive acronym for Caph just Aint Plain Hdl. It is also the name of the second brightest star in the constellation of Cassiopeia.
- 2.
In Fig. 1, streams are denoted (ordered) from right to left; for example, the actor ADD first processes the token 1, then the token 2, etc. Since streams are potentially infinite, their end is denoted “…”. However, when describing actors textually, streams will be denoted from left to right; for example, ADD:1,2,…= 2,3,…
- 3.
Pop the value from the connected FIFO.
- 4.
The ’_’ symbol can also be used in the right-hand side of a rule; it then means that no value is produced on the corresponding output.
- 5.
Synthesis of the generated VHDL code is carried using third-party tools; we currently use the altera Quartus II environment.
- 6.
In the sequel, an instantiated actor will be called a box.
- 7.
This evaluation takes place in an environment augmented with the bindings resulting from the corresponding firing action; for the sake of readability, environments have been left implicit here.
- 8.
It operates by inspecting the general rule format of the actor.
- 9.
Which is part of the compiler options.
- 10.
Hence, pixels are actually encoded on 8 bits (+2 for control) and sums on 16 bits in this example.
- 11.
Dedicated VHDL processes, transparent to the programmer, handle the insertion (resp. removal) of control tokens after (resp. before) the image date is read from (resp. written to) camera (resp. display).
- 12.
It is possible to get rid of this FIFO by inserting a s1f (skip one frame) operator on the corresponding wire. In this case, the bounding boxes computed on frame number i are actually displayed on frame i + 1, which is acceptable if the objects do not move too quickly.
- 13.
Programming these “dataflow computers” then meant writing the code of each DDP and configuring the network interconnections.
- 14.
The dataflow computer described in [17] embedded 1024 DDPs, but it was a dedicated machine, not easily replicated.
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1 Appendix 1: Code Generated by the VHDL Back End for the suml Actor
2 Appendix 2: Code Generated by the SystemC Back End for the suml Actor
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Sérot, J., Berry, F., Ahmed, S. (2013). CAPH: A Language for Implementing Stream-Processing Applications on FPGAs. In: Athanas, P., Pnevmatikatos, D., Sklavos, N. (eds) Embedded Systems Design with FPGAs. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1362-2_9
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