Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC and SVC Video Codecs

  • Andrés Otero
  • Teresa Cervero
  • Eduardo de la Torre
  • Sebastián López
  • Gustavo M. Callicó
  • Teresa Riesgo
  • Roberto Sarmiento
Chapter

Abstract

Systems relying on fixed hardware components with an invariable level of parallelism can suffer from an underuse of their logic resources. This weakness is especially notable when modern applications are implemented using more flexible and adaptable standards, like the latest release of the H.264/AVC, the scalable video coding, which offers several levels of scalability. This chapter presents a scalable architecture where the number of processing elements might be adapted at run time by means of exploiting a run-time variable parallelism throughout the dynamic and partial reconfiguration feature of modern FPGAs. Based on this proposal, a scalable deblocking filter core, compliant with the H.264/AVC and SVC standards, has been designed. This scalable core allows run-time addition or removal of computational units working in parallel. Scalability is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, MB filtering order is modified accordingly. Together with the deblocking filter, a reconfiguration engine suited to highly regular and modular architectures is also presented. Furthermore, the proposed architecture might be exploited as a generic scalable framework for implementing certain kinds of applications following similar parallelism patterns.

Keywords

Entropy 

Notes

Acknowledgements

This chapter is supported by the Spanish Ministry of Science and Innovation and European Union (FEDER funds) in the context of Dynamic Reconfigurability for Scalability in Multimedia Oriented Networks (DR. SIMON) project, under contract TEC2008-065846-C02. On the other hand, the development of the reconfiguration engine was supported by the Artemis program under the project SMART (Secure, Mobile Visual Sensor Networks Architecture) with number ARTEMIS-2008-100032.

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Copyright information

© Springer Science+Business Media, LLC 2013

Authors and Affiliations

  • Andrés Otero
    • 1
  • Teresa Cervero
    • 2
  • Eduardo de la Torre
    • 1
  • Sebastián López
    • 2
  • Gustavo M. Callicó
    • 2
  • Teresa Riesgo
    • 1
  • Roberto Sarmiento
    • 2
  1. 1.CEI, Universidad Politécnica de Madrid, E.T.S.I.Industriales. José Guitérrez Abascal 2MadridSpain
  2. 2.IUMA, Universidad de Las Palmas de Gran CanariaMadridSpain

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