Embedded Systems Start-Up Under Timing Constraints on Modern FPGAs

  • Joachim Meyer
  • Juanjo Noguera
  • Michael Hübner
  • Rodney Stewart
  • Jürgen Becker


In this chapter the authors present advanced techniques, methods, and tool flows that enable embedded systems implemented on FPGAs to start up under tight timing constraints (i.e., hard deadlines). Meeting the application deadline is achieved by exploiting the FPGA programmability in order to implement a two-stage system start-up approach, as well as a suitable memory hierarchy. This reduces the FPGA configuration time as well as the start-up time of the embedded software. Thereby the start-up time for timing-critical parts of a design is neither dependent on the complexity of the complete system nor on the start-up time of the complete system. An automotive case study is used to demonstrate the feasibility and quantify the benefits of the proposed approach.


  1. 1.
    Benavides T, Treon J, Hulbert J, Chang W (2007) The implementation of a hybrid-execute-in-place architecture to reduce the embedded system memory footprint and minimize boot time. In: Information reuse and integration, 2007. IRI 2007. IEEE international conference on, pp 473–479, DOI 10.1109/IRI.2007.4296665Google Scholar
  2. 2.
    Chung KH, Choi MS, Ahn KS (2007) A study on the packaging for fast boot-up time in the embedded linux. In: Embedded and real-time computing systems and applications, 2007. RTCSA 2007. 13th IEEE international conference on, pp 89–94, DOI 10.1109/RTCSA.2007.13Google Scholar
  3. 3.
    Dandalis A, Prasanna V (2005) Configuration compression for fpga-based embedded systems. IEEE Transactions on very large scale integration (VLSI) Systems 13(12):1394–1398. DOI 10.1109/TVLSI.2005.862721Google Scholar
  4. 4.
    Deshpande D, Somani AK, Tyagi A (1999) Configuration caching vs data caching for striped fpgas. In: Proceedings of the 1999 ACM/SIGDA seventh international symposium on field programmable gate arrays, ACM, New York, NY, USA, FPGA ’99, pp 206–214,,
  5. 5.
    Hauck S (1998) Configuration prefetch for single context reconfigurable coprocessors. In: Proceedings of the 1998 ACM/SIGDA sixth international symposium on field programmable gate arrays, ACM, New York, NY, USA, FPGA ’98, pp 65–74,,
  6. 6.
    Huebner M, Meyer J, Sander O, Braun L, Becker J, Noguera J, Stewart R (2010) Fast sequential fpga startup based on partial and dynamic reconfiguration. In: VLSI (ISVLSI), 2010. IEEE computer society annual symposium on, pp 190–194, DOI 10. 1109/ISVLSI.2010.19Google Scholar
  7. 7.
    Li Z, Hauck S (2001) Configuration compression for virtex fpgas. In: Field-programmable custom computing machines, 2001. FCCM ’01. The 9th annual IEEE symposium on, pp 147–159, DOI 10.1109/FPGM.2001.184258Google Scholar
  8. 8.
    Li Z, Compton K, Hauck S (2000) Configuration caching management techniques for reconfigurable computing. In: Proceedings of the 2000 IEEE symposium on field-programmable custom computing machines, IEEE computer society, Washington, DC, USA, FCCM ’00, pp 22
  9. 9.
    Patel P (2006) Embedded systems design using fpga. In: VLSI design, 2006. Held jointly with 5th international conference on embedded systems and design, 19th international conference on, p 1 DOI 10.1109/VLSID.2006.83Google Scholar
  10. 10.
    PCI-SIG (2005) PCI Express base specification, REV. 1.1. PCI-SIGGoogle Scholar
  11. 11.
    Schiefer A, Kebschull U (2005) Optimization of start-up time and quiescent power consumption of fpgas. In: Field programmable logic and applications, 2005. International conference on, pp 551–554, DOI 10.1109/FPL.2005.1515783Google Scholar
  12. 12.
    Sellers B, Heiner J, Wirthlin M, Kalb J (2009) Bitstream compression through frame removal and partial reconfiguration. In: Field programmable logic and applications, 2009. FPL 2009. International conference on, pp 476–480, DOI 10.1109/FPL.2009. 5272502Google Scholar
  13. 13.
    Stefan R, Cotofana S (2008) Bitstream compression techniques for virtex 4 fpgas. In: Field programmable logic and applications, 2008. FPL 2008. International conference on, pp 323–328, DOI 10.1109/FPL.2008.4629952Google Scholar
  14. 14.
    Wu CH (2008) A time-predictable system initialization design for huge-capacity flash-memory storage systems. In: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, ACM, New York, NY, USA, CODES+ISSS ’08, pp 13–18,,
  15. 15.
    Xilinx (2009) Virtex-5 FPGA configuration user guide, UG191, v3.8. Available at
  16. 16.
    Xilinx (2010a) Fast configuration of PCI express technology through partial reconfiguration, XAPP883, v1.0. Available at
  17. 17.
    Xilinx (2010b) Hierarchical design methodology guide, UG748, v12.1Google Scholar
  18. 18.
    Xilinx (2010c) Spartan-6 FPGA configuration user guide, UG380, v2.1. Available at
  19. 19.
    Xilinx (2011a) 7 Series FPGAs overview, DS180, v1.5. Available at
  20. 20.
    Xilinx (2011b) MicroBlaze processor reference guide, UG081, v13.3. Available at
  21. 21.
    Xilinx (2011c) Zynq-7000 Extensible processing platform product brief. Available at
  22. 22.
    Yim KS, Kim J, Koh K (2005) A fast start-up technique for flash memory based computing systems. In: Proceedings of the 2005 ACM symposium on applied computing, ACM, New York, NY, USA, SAC ’05, pp 843–849,,

Copyright information

© Springer Science+Business Media, LLC 2013

Authors and Affiliations

  • Joachim Meyer
    • 1
  • Juanjo Noguera
    • 2
  • Michael Hübner
    • 1
  • Rodney Stewart
    • 3
  • Jürgen Becker
    • 1
  1. 1.Karlsruhe Institute of TechnologyKarlsruheGermany
  2. 2.Xilinx Inc.DublinIreland
  3. 3.Xilinx Inc.KillarneyIreland

Personalised recommendations