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Model-based Performance Evaluation of Dynamic Partial Reconfigurable Datapaths for FPGA-based Systems

Chapter

Abstract

Dynamic partial-reconfigurable (DPR) FPGAs have the property that all or part of their functionality can be time-multiplexed at run-time. This is achieved by dynamically transferring partial configuration bitstreams from off-chip memory to FPGA configuration memory via a specialized datapath. The performance of this datapath can have a significant impact on overall system performance and should be considered early in the design cycle. Unfortunately, performance measures for such systems can typically be determined only after development. Such measures are heavily dependent upon the detailed characteristics of the datapath and on the particular workload imposed on the system during measurement and thus can only be used to make predictions for systems similar to that used for initial measurements. In this chapter, we outline an approach to model the DPR datapath early in the design cycle using queueing networks. This modeling approach is essential for experimenting with system parameters and for providing statistical insight into the effectiveness of candidate architectures. A case study is provided to demonstrate the usefulness and flexibility of the modeling scheme.

References

  1. 1.
    Baskett F, Chandy KM, Muntz RR, Palacios FG (1975) Open, closed, and mixed networks of queues with different classes of customers. J ACM 22:248–260. URL DOI http://doi.acm.org/10.1145/321879.321887. URL http://doi.acm.org/10.1145/321879.321887 Google Scholar
  2. 2.
    Bertoli M, Casale G, Serazzi G (2009) Jmt: performance engineering tools for system modeling. SIGMETRICS Perform Eval Rev 36(4):10–15. DOI http://doi.acm.org/10. 1145/1530873.1530877
  3. 3.
    Claus C, Ahmed R, Altenried F, Stechele W (2010) Towards rapid dynamic partial reconfiguration in video-based driver assistance systems. In: ARC, pp 55–67Google Scholar
  4. 4.
    Claus C, Zhang B, Stechele W, Braun L, Hübner M, Becker J (2008) A multi-platform controller allowing for maximum dynamic partial reconfiguration throughput. In: FPL, pp 535–538Google Scholar
  5. 5.
    Galindo J, Peskin E, Larson B, Roylance G (2008) Leveraging firmware in multichip systems to maximize fpga resources: an application of self-partial reconfiguration. In: Proceedings of the 2008 international conference on reconfigurable computing and FPGAs, pp 139–144. IEEE Computer Society, Washington, DC, USA DOI 10.1109/ReConFig.2008.81. URL http://portal.acm.org/citation.cfm?id=1494647.1495194
  6. 6.
    Griese B, Vonnahme E, Porrmann M, Rückert U (2004) Hardware support for dynamic reconfiguration in reconfigurable soc architectures. In: FPL, pp 842–846Google Scholar
  7. 7.
    Gross D, Harris CM (1985) Fundamentals of queueing theory, 2nd edn. Wiley, New YorkGoogle Scholar
  8. 8.
    Hsiung PA, Lin CS, Liao CF (2008) Perfecto: a systemc-based design-space exploration framework for dynamically reconfigurable architectures. ACM Trans Reconfigurable Technol Syst 1:17:1–17:30Google Scholar
  9. 9.
    Jackson JR (1957) Networks of waiting lines. Oper Res 5(4):518–521. URL http://www.jstor.org/stable/167249 Google Scholar
  10. 10.
    Papadimitriou K, Dollas A, Hauck S (2011) Performance of partial reconfiguration in FPGA systems: A survey and a cost model. ACM Trans Reconfigurable Technol Syst 4:36:1–36:24. New York, NY, USA. URL http://doi.acm.org/10.1145/2068716.2068722
  11. 11.
    Pattipati KR, Kostreva MM, Teele JL (1990) Approximate mean value analysis algorithms for queuing networks: existence, uniqueness, and convergence results. J ACM 37:643–673. DOI http://doi.acm.org/10.1145/79147.214074. URL http://doi.acm.org/10.1145/79147.214074 Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2013

Authors and Affiliations

  1. 1.School of EngineeringThe University of British ColumbiaColumbiaCanada

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