Lifetime Reliability Sensing in Modern FPGAs

  • Abdulazim AmouriEmail author
  • Mehdi Tahoori


Transistor aging due to negative bias temperature instability (NBTI) and hot carrier injection (HCI) is a major reliability issue for aggressive device downscaling at nanoscale. State-of-the-art FPGA chips, which use most recent CMOS technologies and smallest feature sizes to meet high-performance demands, are at the front line to face this problem. In this chapter, we present the design and mapping of a low-cost logic-level aging sensor for FPGA-based designs. The mapping of this sensor is designed to provide controlled sensitivity, ranging from a warning sensor to a late transition detector. We also provide a selection scheme to determine the most aging-critical paths at which the sensor should be placed. The functionality of the sensor has been verified on a Virtex-5-based board. Area, delay, and power overhead of a set of sensors mapped for most aging-critical paths of representative designs are very modest (≈1.3% area,≈1.6% performance, and≈1.5% power overhead).


Clock Cycle Critical Path Path Delay Detection Window Aging Sensor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



The authors would like to thank both Saman Kiamehr, and Fabian Oboril, from Karlsruhe Institute of Technology (KIT), for the very helpful discussions regarding the selection schemes of the paths to be monitored.


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© Springer Science+Business Media, LLC 2013

Authors and Affiliations

  1. 1.Chair of Dependable Nano Computing (CDNC)Karlsruhe Institute of Technology (KIT)KarlsruheGermany

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