Advertisement

Lifetime Reliability Sensing in Modern FPGAs

  • Abdulazim AmouriEmail author
  • Mehdi Tahoori
Chapter

Abstract

Transistor aging due to negative bias temperature instability (NBTI) and hot carrier injection (HCI) is a major reliability issue for aggressive device downscaling at nanoscale. State-of-the-art FPGA chips, which use most recent CMOS technologies and smallest feature sizes to meet high-performance demands, are at the front line to face this problem. In this chapter, we present the design and mapping of a low-cost logic-level aging sensor for FPGA-based designs. The mapping of this sensor is designed to provide controlled sensitivity, ranging from a warning sensor to a late transition detector. We also provide a selection scheme to determine the most aging-critical paths at which the sensor should be placed. The functionality of the sensor has been verified on a Virtex-5-based board. Area, delay, and power overhead of a set of sensors mapped for most aging-critical paths of representative designs are very modest (≈1.3% area,≈1.6% performance, and≈1.5% power overhead).

Keywords

Clock Cycle Critical Path Path Delay Detection Window Aging Sensor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgements

The authors would like to thank both Saman Kiamehr, and Fabian Oboril, from Karlsruhe Institute of Technology (KIT), for the very helpful discussions regarding the selection schemes of the paths to be monitored.

References

  1. 1.
    Iwai H (2009) Technology roadmap for 22 nm and beyond. In: Electron devices and semiconductor technology, 2nd international workshop on 2009. IEDST ’09, pp 1–4Google Scholar
  2. 2.
    Borkar S (2007) Thousand core chips: a technology perspective, In: DAC ’07: Proceedings of the 44th annual design automation conference. ACM, New York, NY, USA, pp 746–749Google Scholar
  3. 3.
    Borkar S (2009) Design perspectives on 22 nm cmos and beyond. In: DAC ’09: Proceedings of the 46th annual design automation conference. ACM, New York, NY, USA, pp 93–94Google Scholar
  4. 4.
    Borkar S (2006) Tackling variability and reliability challenges. IEEE Des Test Comput 23:520CrossRefGoogle Scholar
  5. 5.
    Park SP, Kang K, Roy K (2009) Reliability implications of bias-temperature instability in digital ics. IEEE Des Test 26(6):8–17CrossRefGoogle Scholar
  6. 6.
    Bernstein K, Frank DJ, Gattiker AE, Haensch W, Ji BL, Nassif SR, Nowak EJ, Pearson DJ, Rohrer NJ (2006) High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res Dev Adv Silicon Tech 50:433–449CrossRefGoogle Scholar
  7. 7.
    Stott EA, Wong JS, Sedcole P, Cheung PY (2010) Degradation in fpgas: measurement and modelling. In: FPGA ’10: Proceedings of the 18th annual ACM/SIGDA international symposium on field programmable gate arrays. ACM, New York, NY, USA, pp 229–238Google Scholar
  8. 8.
    Tiwari A, Torrellas J (2008) Facelift: Hiding and slowing down aging in multicores. In: 2008 41st IEEE/ACM international symposium on microarchitecture, 2008. MICRO-41, pp 129–140Google Scholar
  9. 9.
    Zick KM, Hayes JP (2010) On-line sensing for healthier fpga systems. In: FPGA ’10: Proceedings of the 18th annual ACM/SIGDA international symposium on field programmable gate arrays. ACM, New York, NY, USA, pp 239–248Google Scholar
  10. 10.
    Mangalagiri P, Bae S, Krishnan R, Xie Y, Narayanan V (2008) Thermal-aware reliability analysis for platform fpgas. In: ICCAD ’08: Proceedings of the 2008 IEEE/ACM international conference on computer-aided design. IEEE Press, Piscataway, NJ, USA, pp 722–727Google Scholar
  11. 11.
    Wang W, Reddy V, Krishnan A, Vattikonda R, Krishnan S, Cao Y (2007) Compact modeling and simulation of circuit reliability for 65-nm cmos technology. IEEE Trans Device Mater Reliab 7(4):509–517CrossRefGoogle Scholar
  12. 12.
    Zafar S, Kim Y, Narayanan V, Cabral C, Paruchuri V, Doris B, Stathis J, Callegari A, Chudzik M (2006) A comparative study of nbti and pbti (charge trapping) in sio2/hfo2 stacks with fusi, tin, re gates. In: 2006 symposium on VLSI technology, 2006. Digest of technical papers. IEEE, New York, pp 23–25Google Scholar
  13. 13.
    Bhardwaj S, Wang W, Vattikonda R, Cao Y, Vrudhula S (2006) Predictive modeling of the nbti effect for reliable design. In: Custom integrated circuits conference, CICC’06. IEEE, New York, pp 189–192Google Scholar
  14. 14.
    Kim J, Rao R, Mukhopadhyay S, Chuang C (2008) Ring oscillator circuit structures for measurement of isolated nbti/pbti effects. In: IEEE international conference on integrated circuit design and technology and tutorial, ICICDT. IEEE, New York, pp 163–166Google Scholar
  15. 15.
    Stathis JH, Wang M, Zhao K (2010) Reliability of advanced high-k/metal-gate n-FET devices. Microelectronics Reliability, Elsevier, 50(9–11):1199–1202CrossRefGoogle Scholar
  16. 16.
    Wang W, Yang S, Bhardwaj S, Vrudhula S, Liu F, Cao Y (2010) The impact of nbti effect on combinational circuit: modeling, simulation, and analysis. IEEE Trans VLSI Syst 18(2):173–183CrossRefGoogle Scholar
  17. 17.
    Renesas (2008) Semiconductor reliability handbook. Renesas Electronics Corporation, JapanGoogle Scholar
  18. 18.
  19. 19.
    Abramovici M, Stroud CE (2003) Bist-based delay-fault testing in fpgas. J Electron Test 19(5):549–558CrossRefGoogle Scholar
  20. 20.
    Wong J, Cheung P (2011) Improved delay measurement method in fpga based on transition probability. In: Proceedings of the 19th ACM/SIGDA international symposium on field programmable gate arrays. ACM, New York, pp 163–172Google Scholar
  21. 21.
    Srinivasan S, Mangalagiri P, Xie Y, Vijaykrishnan N, Sarpatwari K (2006) Flaw: Fpga lifetime awareness. In: DAC ’06: Proceedings of the 43rd annual design automation conference. ACM, New York, pp 630–635Google Scholar
  22. 22.
    Stott E, Wong J, Cheung P (2010) Degradation analysis and mitigation in fpgas. In: 2010 international conference on field programmable logic and applications (FPL), pp 428–433Google Scholar
  23. 23.
    Keane J, Kim T, Wang X, Kim CH (2010) On-chip reliability monitors for measuring circuit degradation. Microelectronics Reliability, Elsevier, 50(8):1039–1053CrossRefGoogle Scholar
  24. 24.
    Omana M, Rossi D, Bosio N, Metra C (2010) Novel low-cost aging sensor. In: CF ’10: Proceedings of the 7th ACM international conference on Computing frontiers. ACM, New York, pp 93–94Google Scholar
  25. 25.
    Ernst D, Kim NS, Das S, Pant S, Rao R, Pham T, Ziesler C, Blaauw D, Austin T, Flautner K, and others (2003) Razor: A low-power pipeline based on circuit-level timing speculation. Microarchitecture, 2003, MICRO-36. Proceedings 36th Annual IEEE/ACM International Symposium on, IEEE, pp 7–18Google Scholar
  26. 26.
    Sato T, Kunitake Y (2007) A simple flip-flop circuit for typical-case designs for DFM. Quality Electronic Design, 2007. ISQED’07. 8th International Symposium on, IEEE, pp 539–544Google Scholar
  27. 27.
    Eireiner M, Henzler S, Georgakos G, Berthold J, Schmitt D-Landsiedel (2007) In-situ delay characterization and local supply voltage adjustment for compensation of local parametric variations. IEEE J Solid State Circ 42(7):1583–1592CrossRefGoogle Scholar
  28. 28.
    Das S, Tokunaga C, Pant S, Ma W-H, Kalaiselvan S, Lai K, Bull D, Blaauw D (2009) Razorii: in situ error detection and correction for pvt and ser tolerance. IEEE J Solid State Circ 44(1):32–48CrossRefGoogle Scholar
  29. 29.
    Bowman K, Tschanz J, Kim NS, Lee J, Wilkerson C, Lu S-L, Karnik T, De V (2009) Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance. IEEE J Solid State Circ 44(1):49–63CrossRefGoogle Scholar
  30. 30.
    Xilinx synthesis and simulation design guide. http://www.xilinx.com
  31. 31.
    Noda M, Kajihara S, Sato Y, Miyase K, Wen X, Miura Y (2010) On estimation of nbti-induced delay degradation. In: 2010 15th IEEE European Test Symposium (ETS), pp 107–111Google Scholar
  32. 32.
    Wang W, Yang S, Bhardwaj S, Vrudhula S, Liu F, Cao Y (2010) The impact of nbti effect on combinational circuit: modeling, simulation, and analysis. IEEE Trans VLSI Syst 18(2):173–183CrossRefGoogle Scholar
  33. 33.
    Takeda E, Suzuki N (1983) An empirical model for device degradation due to hot-carrier injection. IEEE Electron Device Lett 4(4):111–113CrossRefGoogle Scholar
  34. 34.
    Angermeier J, Amouri A, Teich J (2009) General methodology for mapping iterative approximation algorithms to adaptive dynamically partially reconfigurable systems. In: International conference on field programmable logic and applications, FPL 2009, pp 302–307CrossRefGoogle Scholar
  35. 35.
    Opencores. http://opencores.org. Accessed 2011

Copyright information

© Springer Science+Business Media, LLC 2013

Authors and Affiliations

  1. 1.Chair of Dependable Nano Computing (CDNC)Karlsruhe Institute of Technology (KIT)KarlsruheGermany

Personalised recommendations