Compact CLEFIA Implementation on FPGAs
In this chapter two compact hardware structures for the computation of the CLEFIA encryption algorithm are presented. One structure based on the existing state of the art and a novel structure with a more compact organization. The implementation of the 128-bit input key scheduling in hardware is also herein presented. This chapter shows that, with the use of the existing embedded FPGA components and a careful scheduling, throughputs above 1 Gbit/s can be achieved with a resource usage as low as 238 LUTs and 3 BRAMs on a Virtex 4 FPGA. Implementation results suggest that a LUT reduction up to 60 % can be achieved at a performance cost of 15 % on a Virtex 4 FPGA, resulting in throughput/slice efficiency gains up to 2.25 times, when compared with the related state of the art. Results also suggest that the implementation of the key scheduling in hardware imply an increase of up to 100 % of the needed area resources but without significantly affecting the ciphering throughput.
KeywordsData Path Pipeline Stage Digital Right Management Hardware Structure Diffusion Matrice
This work was supported by the Portuguese Foundation for Science and for Technology (INESC-ID multi-annual funding) through the PIDDAC Program funds and by the QREN Program under contract N o 3487.
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