Automated Generation of Directed Tests

  • Mingsong Chen
  • Xiaoke Qin
  • Heon-Mo Koo
  • Prabhat Mishra
Chapter

Abstract

Due to the increasing complexity coupled with limited time-to-market, functional validation is becoming a major bottleneck in SoC design. Directed testing is recognized as a promising simulation-based validation method, since only a small set of directed tests is required to achieve the desired coverage. However, currently most direct test generation needs human intervention, which is time-consuming and error-prone. Based on the property falsification, this chapter presents a model checking based approach, which can automatically generate directed tests from the SoC models and specifications.

Keywords

Compaction 

References

  1. 1.
    Duran JW, Ntafos SC (1999) An evaluation of random testing. IEEE Trans Softw Eng 10(4):438–444CrossRefGoogle Scholar
  2. 2.
    Fine S, Ziv A (2003) Coverage directed test generation for functional verification using Bayesian networks. In: Proceedings of design automation conference (DAC), pp 286–291Google Scholar
  3. 3.
    Clarke E, Grumberg O, Peled D (1999) Model checking. MIT Press, CambridgeGoogle Scholar
  4. 4.
    Bryant R (1986) Graph-based algorithms for boolean function manipulation. IEEE Comput Soc 35(8):677–691MATHCrossRefGoogle Scholar
  5. 5.
    Prasad M, Biere A, Gupta A (2005) A survey of recent advances in SAT-based formal verification. Int J Softw Tools Technol Transf 7(2):156–173CrossRefGoogle Scholar
  6. 6.
    Biere A, Cimatti A, Clarke E. M., Zhu Y (1999) Symbolic model checking without BDDs. In: Proceedings of tools and algorithms for the construction and analysis of systems (TACAS) pp 193–207Google Scholar
  7. 7.
    Biere A, Cimatti A, Clarke EM (2003) Bounded model checking. Adv Comput 58(3):117–148Google Scholar
  8. 8.
    Wagner I, Bertacco V, Austin T (2005) StressTest: An automatic approach to test generation via activity monitors. In: Proceedings of design automation conference (DAC), pp 783–788Google Scholar
  9. 9.
    Adir A, Almog E, Fournier L, Marcus E, Rimon M, Vinov M, Ziv A (2004) Genesys-pro: Innovations in test program generation for functional processor verification. IEEE Des Test 21(2):84–93CrossRefGoogle Scholar
  10. 10.
    Adir A, Bin E, Peled O, Ziv A (2003) A test program generator for micro-architecture flow verification. In: Proceedings of high-level design validation and test workshop (HLDVT), pp 23–28Google Scholar
  11. 11.
    Aharon A, Goodman D, Levinger M, Lichtenstein Y, Malka Y, Metzger C, Molcho M, Shurek G (1995) Test program generation for functional verification of PowerPC processors in IBM. In: Proceedings of design automation conference (DAC), pp 279–285Google Scholar
  12. 12.
    Koo H, Mishra P, Bhadra J, Abadir M (2006) Directed micro-architectural test generation for an industrial processor: A case study. In: Proceedings of microprocessor test and verification (MTV), pp 33–36Google Scholar
  13. 13.
    Ur S, Yadin Y (1999) Micro architecture coverage directed generation of test programs. In: Proceedings of design automation conference (DAC), pp 175–180Google Scholar
  14. 14.
    Gluska A (2006) Practical methods in coverage-oriented verification of the Merom microprocessor. In: Proceedings of design automation conference (DAC), pp 332–337Google Scholar
  15. 15.
    Ammann PE, Black PE, Majurski W (1998) Using model checking to generate tests from specifications. In: Proceedings of international conference on formal engineering methods (ICFEM), pp 46–55Google Scholar
  16. 16.
    Marques-Silva J, Sakallah K (1999) Grasp: a search algorithm for propositional satisfiability. IEEE Trans Comput 48(5):506–521MathSciNetCrossRefGoogle Scholar
  17. 17.
    Goldberg E, Novikov Y (2002) BerkMin: a fast and robust SAT-solver. In: Proceedings of design automation and test in Europe (DATE), pp 142–149Google Scholar
  18. 18.
    Moskewicz M, Madigan C, Zhao Y, Zhang L, Malik S (2001) Chaff: Engineering an efficient SAT solver. In: Proceedings of Design Automation Conference (DAC), pp 530–535Google Scholar
  19. 19.
    Amla N, Du X, Kuehlmann A, Kurshan R, McMillan K (2005) An analysis of SAT-based model checking techniques in an industrial environment. In: Proceedings of correct hardware design and verification methods (CHARME), pp 254–268Google Scholar
  20. 20.
    Copty F, Fix L, Fraer R, Giunchiglia E, Kamhi G, Tacchella A, Vardi M (2001) Benefits of bounded model checking at an industrial setting. In: Proceedings of computer aided verification (CAV), pp 436–453Google Scholar
  21. 21.
    Zhu H, Hall P, May J (1997) Software Unit Test Coverage and Adequacy. ACM Comput Surv 29(4):366–427CrossRefGoogle Scholar
  22. 22.
    Ferrandi F, Fummi F, Gerli L, Sciuto D (1999) Symbolic functional vector generation for VHDL specifications. In: Proceedings of design, automation and test in Europe (DATE), pp 442–446Google Scholar
  23. 23.
  24. 24.
    Koo HM, Mishra P (2009) Functional test generation using design and property decomposition techniques. ACM Trans Embed Comput Syst (TECS) 8(4):32:1–32:33Google Scholar
  25. 25.
    Mishra P, Dutt N (2004) Graph-based functional test program generation for pipelined processors. In: Proceedings of design automation and test in Europe (DATE), pp 182–187Google Scholar
  26. 26.
    Mishra P, Dutt N (2005) Functional coverage driven test generation for validation of pipelined processors. In: Proceedings of design automation and test in Europe (DATE), pp 678–683Google Scholar
  27. 27.
    Koo HM, Mishra P (2006) Test generation using (SAT)-based bounded model checking for validation of pipelined processors. In: Proceedings of ACM great lakes symposium on VLSI (GSLVLSI), pp 362–365Google Scholar
  28. 28.
    Mishra P, Koo HM, Huang Z (2005) Language-driven validation of pipelined processors using satisfiability solvers. In: Proceedings of international workshop on microprocessor test and verification (MTV)), pp 119–126Google Scholar
  29. 29.
    Chen M, Qiu X, Li X (2006) Automatic test case generation for UML activity diagrams. In: Proceedings of international workshop on automation on software test, pp 2–8Google Scholar
  30. 30.
    Chen M, Qiu X, Xu W, Wang L, Zhao J, Li X (2009) UML activity diagram based automatic test case generation for java programs. Comput J 52(5):545–556Google Scholar

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Mingsong Chen
    • 1
  • Xiaoke Qin
    • 2
  • Heon-Mo Koo
    • 3
  • Prabhat Mishra
    • 2
  1. 1.Software Engineering InstituteEast China Normal UniversityShanghaiPeople’s Republic of China
  2. 2.Department of Computer and Information Science and EngineeringUniversity of FloridaGainsvilleUSA
  3. 3.Intel corporationSantaUSA

Personalised recommendations