Conclusions

  • Mingsong Chen
  • Xiaoke Qin
  • Heon-Mo Koo
  • Prabhat Mishra
Chapter

Abstract

Functional validation is widely acknowledged as a major bottleneck in SoC design methodology due to combined effects of increasing design complexity and reduced time-to-market. To reduce validation complexity, it is necessary to develop efficient techniques for high-level validation and automated reuse of validation efforts between abstraction levels. This book presented a top-down methodology for automatically generating directed tests from high-level specifications for functional validation of both specification and implementation. The proposed methodology can drastically reduce the overall design and validation effort of complex SoC architectures. This chapter summarizes the ideas presented in previous chapters and outlines future research directions.

Keywords

Coherence Compaction 

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Mingsong Chen
    • 1
  • Xiaoke Qin
    • 2
  • Heon-Mo Koo
    • 3
  • Prabhat Mishra
    • 2
  1. 1.Software Engineering InstituteEast China Normal UniversityShanghaiPeople’s Republic of China
  2. 2.Department of Computer and Information Science and EngineeringUniversity of FloridaGainsvilleUSA
  3. 3.Intel corporationSantaUSA

Personalised recommendations