Abstract
In a complete physical synthesis flow, many optimizations are applied to critical paths that are already optimized by a series of powerful transformations, as described in Chap. 2. Transforms that can further improve the timing of such paths are invaluable for timing closure. Finding such transformations and applying them efficiently is challenging.
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Notes
- 1.
Without loss of generality, we assume \(n\) and \(m\) are of the same order for simplicity of the complexity analysis.
References
Ku?nar R, Brglez F (1995) PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists. In: ICCAD, pp 644–649
Hwang J, El Gamal A (1992) Optimal replication for min-cut partitioning. In: ICCAD, pp 432–435
Chen G, Cong J (2005) Simultaneous timing-driven placement and duplication. In: ISFPGA, pp 51–59
Kim H, Lillis J, Hrkic M (2006) Techniques for improved placement-coupled logic replication. In: GLSVLSI, pp 211–216
Chen C, Tsui C (1999) Timing optimization of logic network using gate duplication. In: ASP-DAC, pp 233–236
Lillis J, Cheng CK, Lin TY (1996) Algorithms for optimal introduction of redundant logic for timing and area optimization. In: ISCAS, pp 452–455
Srivastava A et al (2001) On the complexity of gate duplication. IEEE Trans CAD 20(9):1170–1176
Srivastava A et al (2004) Timing driven gate duplication. IEEE Trans VLSI 12(1):42–51
Saxena P, Menezes N, Cocchini P, Kirkpatrick DA (2004) Repeater scaling and its impact on CAD. IEEE Trans CAD 23(4):451–463
Bañeres D, Cortadella J, Kishinevsky M (2007) Layout-aware gate duplication and buffer insertion. In: DATE, pp 1367–1372
Alpert CJ et al (2006) Accurate estimation of global buffer delay within a floorplan. IEEE Trans TCAD 25(6):1140–1146
Otten R (1998) Global wires harmful. In: ISPD, pp 104–109
Luo T, Papa DA, Li Z, Sze CN, Alpert CJ, Pan DZ (2008) Pyramids: an efficient computational geometry-based approach for timing-driven placement. In: ICCAD, pp 204–211
Shi W, Li Z, Alpert CJ (2004) Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost. In: ASP-DAC, pp 609–614
Chao TH et al (1992) Zero skew clock routing with minimum wirelength. IEEE Trans CAS 39(11):799–814
Li Z, Sze CN, Alpert CJ, Hu J, Shi W (2005) Making fast buffer insertion even faster via approximation techniques. In: ASP-DAC, pp 13–18
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Papa, D.A., Markov, I.L. (2013). Physically-Driven Logic Restructuring. In: Multi-Objective Optimization in Physical Synthesis of Integrated Circuits. Lecture Notes in Electrical Engineering, vol 166. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1356-1_6
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DOI: https://doi.org/10.1007/978-1-4614-1356-1_6
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