Coprocessor Design Space Exploration Using High Level Synthesis

Abstract

The traditional computing arena of hardware/software co-design has gained importance in the context of system-on-chip design methodologies. Apart from the classic issues of partitioning, communication and granularity, the need for quick estimation of metrices such as area, power, and latency has turned out to be important. This can be attributed to the large design space under consideration. The number of IPs integrated on a system is large and each IP may have multiple configurations. Many of these IPs are often hardware coprocessors that accelerate compute-intensive tasks. A collection of coprocessors chosen based on Pareto optimal points w.r.t. speed, area and power may not necessarily add up to corresponding system level Pareto optimal points [67]. One way to address this issue could be through developing algorithms or heuristics that lead towards Pareto optimal configuration. Obtaining a generic strategy, keeping in mind global optimization, is hard. Furthermore, evolving mathematical models for such diverse systems is very difficult. Another approach involves using partial or full simulation of systems for different configurations. Various standard co-design platforms are available for the same [69, 146]. However, exhaustive design space exploration will be difficult.