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Layout Migration

  • Konstantin Moiseev
  • Avinoam Kolodny
  • Shmuel Wimer
Chapter

Abstract

Designing high-end full-custom VLSI systems such as microprocessors is a very complex engineering task, involving hundreds of man-years’ effort. Hierarchical design methodology is essential for handling the complexity of the task. Fueled by Moore’s Law, market competition and economic considerations dictate the introduction of new products in the so-called “Tick-Tock” strategy. The Tick-Tock development strategy delivers a new product manufactured in the most advanced stable technology (named “old technology”). It is then followed by delivering chips of the same architecture, but in a new, scaled manufacturing process technology (named “new technology”), thus allowing higher production volumes, better performance, and lower cost. An essential part of the second phase is the conversion of the underlying physical layout, comprising billions of polygons, into the new technology. Such conversion is known in VLSI jargon as hard-IP reuse [Nitzan 02]. An enabler for this strategy is therefore the automation of layout conversion from older into newer technology. Such automation is a very challenging computational task that must satisfy complex geometric rules, hence translated into an optimization problem involving billions of variables and constraints.

Keywords

Visibility Graph Constraint Graph Migration Algorithm Positive Cycle Compaction Algorithm 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. [Burns 87]
    J.L. Burns, A.R. Newton, Efficient Constraint Generation for Hierarchical Compaction, IEEE International Conference on Computer Design, pp. 197–200, Oct. 1987.Google Scholar
  2. [Burns 98]
    J.L. Burns, J A. Feldman, C5M – A Control-Logic Layout Synthesis System for High-Performance Microprocessors, IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 17, No. 1, 1998, pp. 14–13.CrossRefGoogle Scholar
  3. [Klau 99]
    G. Klau and P. Mutzel, Optimal compaction of orthogonal grid drawings, Lecture Notes in Computer Science: Integer Programming and Combinatorial Optimization, Vol. 1610, pp 304–319, Springer, 1999.Google Scholar
  4. [Lengauer 84]
    T. Lengauer, On the solution of inequality systems relevant to IC-layout, Journal of Algorithms, Vol. 5, No. 3, 1984, pp. 408–421.CrossRefzbMATHMathSciNetGoogle Scholar
  5. [Lengauer 90]
    T. Lengaur, Combinatorial Algorithms for Integrated Circuit Layout, Chapter 10: Compaction, pp. 579–643, John Wiley, 1990.Google Scholar
  6. [Nitzan 02]
    R. Nitzan and S. Wimer, AMPS and SiClone integration for implementing 0.18 um to 0.13 um design migration, Synoposys Users Group (SNUG) Conf., San Jose CA, March 2002.Google Scholar
  7. [Patrignani 01]
    M. Patrignani, On the complexity of orthogonal compaction, Computational Geometry, Vol. 19, Issue 1, June 2001, pp. 47–67.Google Scholar
  8. [Reinhardt 02]
    M. Reinhardt, Automatic Layout Modification: Including Design Reuse of the Alpha CPU in 0.13 Micron SOI Technology, Kluwer Academic Publishers, 2002.Google Scholar
  9. [Schlag 83]
    M. Schlag, Y. Z. Liao and C.K. Wong, An algorithm for optimal two-dimensional compaction of VLSI layouts, Integration, the VLSI Journal, Vol. 1, Issues 2–3, Oct. 1983, pp. 179–209.Google Scholar
  10. [Shin 86]
    H. Shin, A. L. Sangiovanni-Vincentelli and C. H. Siquin, Two-dimensional compaction by zone refining, Proceeding of the 23rd ACM/IEEE Design Automation Conference, 1986, pp. 115–122.Google Scholar
  11. [Wang 01]
    L-Y. Wang, Y-T Lai, Graph-Theory-Based Simplex Algorithm for VLSI Layout Spacing Problems with Multiple Variables Constraints, IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 20, No. 8, 2001, pp. 967–979Google Scholar
  12. [Wimer 13]
    S. Wimer, “Planar CMOS to multi-gate layout conversion for maximal fin utilization”, Integration, the VLSI Journal (2013).Google Scholar
  13. [Yao 93]
    S-Z. Yao, C-K. ChengT, D. Dutt, S. Nahar, C-Y. Lo, Cell-Based Hierarchical Pitch matching Compaction Using Minimal LP, 30th Design Automation Conf., 1993, pp. 395–400.Google Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Konstantin Moiseev
    • 1
  • Avinoam Kolodny
    • 2
  • Shmuel Wimer
    • 3
  1. 1.IntelHaifaIsrael
  2. 2.TechnionHaifaIsrael
  3. 3.Bar-Ilan UniversityRamat-GanIsrael

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