Interconnect Optimization by Net Ordering

  • Konstantin Moiseev
  • Avinoam Kolodny
  • Shmuel Wimer


Spacing and wire-sizing optimizations, which do not change the topology of the layout, have been discussed in this work so far. The spacing and sizing are based on improving the distribution of the shared white space left by the routing tools between adjacent wires. Such optimizations do not explore the additional degree of freedom in interconnect optimization: wire/net ordering. This is discussed in this chapter, in which the additional optimization potential that can be achieved by reordering of the wires, is applied together with spacing and sizing. Net ordering is advantageous for optimization objectives, such as delay, power, and noise.


Travel Salesman Problem Optimal Order Quadratic Assignment Problem Capacitive Load Wire Sizing 
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  1. [Burkard 98]
    R. E. Burkard, E. Cela, G. Rote and G. J. Woeginger, “The quadratic assignment problem with monotone anti-Monge and symmetric Toeplitz matrix: easy and hard cases,” Mathematical Programming, Vol. 82, 1998, pp. 125–158.Google Scholar
  2. [Deineko 06]
    V. Deineko, B. Klinz and G. J. Woeginger, “Four Point Conditions and Exponential Neighborhoods for Symmetric TSP,” SODA ’06, January 22–26, Miami, FL.Google Scholar
  3. [Demidenko 06]
    V. M. Demidenko, G. Finke and V. S. Gordon, “Well solvable cases of the quadratic assignment problem with monotone and bimonotone matrices,” Journal of Mathematical Modeling and Algorithms, 2006, pp. 167–197.Google Scholar
  4. [Emanuel 11]
    B. Emanuel, S. Wimer and G. Wolansky, “Using well-solvable quadratic assignment problems for VLSI interconnect applications,” Discrete Applied Mathematics, 2011, doi: 10.1016/j.dam.2011.11.017Google Scholar
  5. [Gritzmann 10]
    P. Gritzmann, M. Ritter and P. Zuber, “Optimal wire ordering and spacing in low power semiconductor design,” Mathematical Programming, Vol. 121, No. 2, 2010, pp. 201–220.CrossRefzbMATHMathSciNetGoogle Scholar
  6. [Kahng 99]
    A. B. Kahng, S. Muddu and D. Vidhani, "Noise and Delay Uncertainty Studies for Coupled RC Interconnects", IEEE International ASIC/SOC Conference, September 1999, pp. 3–8.Google Scholar
  7. [Kaul 02]
    Himanshu Kaul, Dennis Sylvester, and David Blaauw. 2002. Active shields: a new approach to shielding global wires. In Proceedings of the 12th ACM Great Lakes symposium on VLSI(GLSVLSI '02). ACM, New York, NY, USA, 112–117. DOI=10.1145/505306.505331 Scholar
  8. [Lawler 85]
    E.L. Lawler, J.K. Lenstra, Rinnooy Kan, and D.B. Shmoys, The Traveling Salesman Problem, Wiley, Chichester, 1985.Google Scholar
  9. [Macii 03]
    E. Macii, M. Poncino and S. Salerno, “Combining wire swapping and spacing for low-power deep submicron buses”, In Proceeding of the 13th ACM Great Lakes Symposium on VLSI, pp. 198–202, 2003.Google Scholar
  10. [Magen 04]
    N. Magen, A. Kolodny, U. Weiser and N. Shamir, “Interconnect power dissipation in a microprocessor”, International Workshop on System Level Interconnect Prediction, pp. 7–13, 2004.Google Scholar
  11. [Moiseev 08a]
    K. Moiseev, S. Wimer and A. Kolodny, “On optimal ordering of signals in parallel wire bundles,” Integration – the VLSI Journal, Vol. 41, 2008, pp. 253–268.CrossRefGoogle Scholar
  12. [Moiseev 08b]
    K. Moiseev, A. Kolodny and S. Wimer, “Timing-Aware Power-Optimal Ordering of Signals,” ACM Transactions on Design Automation of Electronic Systems, Vol. 13, No. 4, Sept. 2008.Google Scholar
  13. [Sato 03]
    T. Sato, Y. Cao, K. Agarwal, D. Sylvester, and C. Hu, "Bidirectional Closed-Form Transformation Between On-Chip Coupling Noise Waveforms and Interconnect Delay-Change Curves", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 560–572, March 2003.Google Scholar
  14. [Sundaresan 05]
    Sundaresan, Krishnan, and Nihar R. Mahapatra. “Accurate energy dissipation and thermal modeling for nanometer-scale buses.” High-Performance Computer Architecture, 2005. HPCA-11. 11th International Symposium on. IEEE, 2005.Google Scholar
  15. [Supnick 57]
    F. Supnick, “Extreme Hamiltonian lines,” Annals of Math., 66 (1957), pp. 179–201.CrossRefzbMATHMathSciNetGoogle Scholar
  16. [Vittal 99]
    A. Vittal, LH. Chen, M. Marek-Sadowska, KP. Wang and S. Yang, “Crosstalk in VLSI interconnections”, IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, Vol. 18, No. 12, Dec 1999, pp. 1817–1824.Google Scholar
  17. [Wimer 11]
    S. Wimer, K. Moiseev, A. Kolodny, “On VLSI interconnect optimization and linear ordering problem, Optimization and Engineering,” No. 12, 2011, pp. 603–609.Google Scholar
  18. [Woeginger 03]
    G. J. Woeginger. “Computational problems without computation,” Nieuwarchief 5 (4), June 2003, pp. 140–147.Google Scholar
  19. [Zuber 09]
    P. Zuber, O. Bahlous, T. Ilnseher, M. Ritter, and W. Stechele, “Wire Topology Optimization for Low Power CMOS,” IEEE Trans. on VLSI Systems, Vol. 17, No. 1, Jan 2009, pp. 1–11.Google Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Konstantin Moiseev
    • 1
  • Avinoam Kolodny
    • 2
  • Shmuel Wimer
    • 3
  1. 1.IntelHaifaIsrael
  2. 2.TechnionHaifaIsrael
  3. 3.Bar-Ilan UniversityRamat-GanIsrael

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